Method and apparatus for testing bumped die

Abstract

An apparatus for testing unpackaged semiconductor dice having raised ball contact locations is disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the ball contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

1 . A bump substrate for use during the testing of a semiconductor die having bond pads having a raised contact bumps thereon extending above a surface of said semiconductor die comprising: 
 a bump substrate having a plurality of contact bump receiving sites formed therein, each of said plurality of contact bump receiving sites having a plurality of sidewalls and a bottom and having a plurality of conductive traces located on at least portions of said plurality of sidewalls thereof for contacting a plurality of conductive traces on said bump substrate and for contacting a corresponding contact bump of said contact bumps on said bond pads received at said plurality of contact bump receiving sites, a conductive trace of said plurality of conductive traces extending along at least a portion of a sidewall of said plurality of sidewalls of a contact receiving site and at least one other conductive trace of said plurality of conductive traces extending along at least a portion of another sidewall of said plurality of sidewalls and a portion of said bottom of said contact receiving site, said plurality of conductive traces forming a plurality of rows and a plurality of columns interconnecting each contact bump receiving site of said plurality of contact bump receiving sites to at least one adjacent contact bump receiving site of said plurality of contact bump receiving sites in an adjacent row of the plurality of rows and an adjacent column of the plurality of columns.    
   
   
       2 . The bump substrate according to  claim 1 , wherein said plurality of contact bump receiving sites comprise pits fabricated in said bump substrate, each pit of said pits having opposing walls wherein said plurality of conductive traces extend down said opposing walls and are free from contact with each other.  
   
   
       3 . An apparatus for testing for the presence of a ball in a plurality of balls located on the bond pads of a semiconductor die, comprising: 
 a signal processor; and    a bump wafer connected to said signal processor, comprising: 
 a plurality of contact points formed in a semiconductor substrate having a pattern essentially corresponding to a pattern of said plurality of balls on said semiconductor die;  
 a plurality of metal traces fabricated on said semiconductor substrate for at least one of said contact points such that the placement of a contact ball on said at least one contact point connects one of said first plurality of traces to a second of said plurality of said traces.  
   
   
   
       4 . The apparatus according to  claim 3 , wherein said plurality of metal traces form an array of rows and columns interconnecting at least one of said contact sites to at least one adjacent contact site.  
   
   
       5 . The apparatus according to  claim 3 , wherein said contact sites comprise pits fabricated in said semiconductor substrate, each pit having opposing walls wherein some of said plurality of metal traces extend down said opposing walls without contacting one another.  
   
   
       6 . The apparatus according to  claim 3 , wherein said plurality of contact sites comprise: 
 a plurality of risers, over which said such plurality of metal traces extend; and    a plurality of blades, situated between the said plurality of rises, to pierce an oxide layer on said contact ball.    
   
   
       7 . The apparatus according to  claim 3 , wherein at least one contact location of said plurality of contact locations comprises: 
 a plurality of retaining posts, over each of which extends one of said metal traces and in which a bump seat is formed for receiving said contact bump.    
   
   
       8 . The apparatus according to  claim 3 , wherein said signal processor selectively applies and senses an electrical current to each of said metal traces.  
   
   
       9 . A method of forming a bump plate from a semiconductor substrate for receiving a plurality of contact bumps on a semiconductor die, the method comprising: 
 forming a plurality of contact bump receiving sites in said bump plate to correspond to a pattern established by a said plurality of contact bumps on said semiconductor die, at least one of said plurality of contact bump receiving sites having a plurality sidewalls; and    forming a plurality of a conductive traces on said substrate and said sidewalls for at least one contact site of said plurality of contact bump receiving sites to contact with a corresponding contact bump of said plurality of contact bumps received at said contact site.    
   
   
       10 . The method according to  claim 9 , wherein said forming a plurality of contact bump receiving sites in said bump plate comprises: 
 applying a photo resist layer on said substrate;    exposing selected regions of said photo resist layer;    removing said exposed photo resist layer regions; and,    etching said removed regions to form said sidewalls in each of said plurality of contact receiving sites.    
   
   
       11 . The method according to  claim 9 , wherein said forming a plurality of a conductive traces on said substrate and said sidewalls comprises: 
 applying a photo resist layer to said substrate;    exposing selected regions of said photo resist layer to form conductive trace patterns on said substrate;    removing said exposed photo resist layer regions; and.    forming a metal trace in said removed photo resist layer regions extending down each of said sidewalls of said plurality of contact receiving sites.    
   
   
       12 . The method according to  claim 9 , wherein said plurality of conductive traces form an array of rows and columns interconnecting each contact site to at least one adjacent contact site.  
   
   
       13 . The method according to  claim 9 , wherein said contact sites comprise a plurality of pits fabricated in a semiconductor substrate having opposing walls having at least two of said plurality of conductive traces extending down said opposing walls of a pit without contacting one another.  
   
   
       14 . The method according to  claim 9 , wherein said forming a plurality of contact bump receiving sites in said bump plate comprises: 
 applying a photo resist layer on said substrate;    exposing selected regions of said photo resist layer;    removing said exposed photo resist layer regions;    forming a plurality of risers in said removed regions; and, 
 forming a plurality of blades, situated between said plurality of risers.  
   
   
   
       15 . The method according to  claim 9 , wherein said forming a plurality of a conductive traces on said substrate and said sidewalls comprises: 
 applying a photo resist layer to said substrate;    exposing selected regions of said photo resist layer to form conductive trace patterns on said substrate;    removing said exposed photo resist layer regions; and.    forming a metal trace in said removed photo resist layer regions extending over each of said plurality of risers.    
   
   
       16 . The method according to  claim 9 , wherein said forming a plurality of contact bump receiving sites in said bump plate comprises: 
 applying a photo resist layer on said substrate;    exposing selected regions of said photo resist layer;    removing said exposed photo resist layer regions; and    forming a plurality of retaining posts in said removed regions.    
   
   
       17 . The method according to  claim 16 , wherein said forming a plurality of a conductive traces on said substrate and said sidewalls for at least one contact site of said plurality of contact bump receiving sites comprises: 
 applying a photo resist layer to said substrate;    exposing selected regions of said photo resist layer to form conductive trace patterns on said substrate;    removing said exposed photo resist layer regions; and.    forming a metal trace in said removed photo resist layer regions extending over each of said plurality of retaining posts.