Recessed-type field effect transistor with reduced body effect

Abstract

For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.

1 . A field effect transistor, comprising: 
 a gate electrode filling an opening formed within a semiconductor substrate;    a gate insulator formed at walls of the opening; and    an extra-doped channel region abutting the gate insulator at a bottom portion of the opening.    
   
   
       2 . The field effect transistor of  claim 1 , further comprising: 
 a drain and a source formed in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.    
   
   
       3 . The field effect transistor of  claim 2 , wherein a conductivity type of a dopant within the extra-doped channel region is opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode.  
   
   
       4 . The field effect transistor of  claim 2 , further comprising: 
 a respective line pad disposed on each of the drain and the source.    
   
   
       5 . The field effect transistor of  claim 4 , wherein the field effect transistor is part of a DRAM (dynamic random access memory) cell.  
   
   
       6 . The field effect transistor of  claim 5 , wherein the respective line pad disposed on the source is coupled to a storage capacitor of the DRAM cell.  
   
   
       7 . The field effect transistor of  claim 5 , wherein the gate electrode forms a word line for the DRAM cell.  
   
   
       8 . The field effect transistor of  claim 1 , further comprising: 
 a gate capping layer disposed on the gate electrode; and    spacers disposed on sidewalls of the gate electrode and the gate capping layer.    
   
   
       9 . The field effect transistor of  claim 1 , further comprising: 
 a STI (shallow trench isolation) structure for defining an active region having the opening formed therein.    
   
   
       10 . The field effect transistor of  claim 1 , wherein the extra-doped channel region abuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening.  
   
   
       11 . A method for fabricating a field effect transistor, comprising: 
 forming an extra-doped channel region below a surface of a semiconductor substrate;    forming an opening in the semiconductor substrate into the extra-doped channel region;    forming a gate insulator at walls of the opening such that the extra-doped channel region abuts the gate insulator at the bottom portion of the opening; and    filling the opening with a gate electrode.    
   
   
       12 . The method of  claim 11 , wherein the extra-doped channel region abuts the gate insulator at a bottom wall and sidewalls of the opening below a half-height of the opening.  
   
   
       13 . The method of  claim 11 , wherein the opening is formed after the extra-doped channel region is formed.  
   
   
       14 . The method of  claim 11 , further comprising: 
 forming a drain and a source in the semiconductor substrate to the sides of the opening with an overlap under the gate insulator and the gate electrode.    
   
   
       15 . The method of  claim 14 , wherein a conductivity type of a dopant within the extra-doped channel region is opposite to a respective conductivity type of a respective dopant in each of the drain, the source, and the gate electrode.  
   
   
       16 . The method of  claim 14 , further comprising: 
 forming a respective line pad on each of the drain and the source.    
   
   
       17 . The method of  claim 16 , further comprising: 
 forming the field effect transistor as part of a DRAM (dynamic random access memory) cell.    
   
   
       18 . The method of  claim 17 , wherein the respective line pad disposed on the source is coupled to a storage capacitor of the DRAM cell, and wherein the gate electrode forms a word line for the DRAM cell.  
   
   
       19 . The method of  claim 11 , further comprising: 
 forming a gate capping layer on the gate electrode; and    forming spacers on sidewalls of the gate electrode and the gate capping layer.    
   
   
       20 . The method of  claim 11 , further comprising: 
 forming a STI (shallow trench isolation) structure for defining an active region having the opening formed therein.