Signal pin tester for AC defects in integrated circuits

Abstract

A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.

1 . A semiconductor test apparatus for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects comprising; 
 a tester having a first and second sets of test contacts thereon; and    a data interface board having a first and second sets of sockets thereon for receiving first and second sets of input/output pins of an integrated circuit, said first set of sockets, on said board, being connected to said first set of input/output pins on said integrated circuit and said second set of sockets, on said board, being connected to said second set of input/output pins on said integrated circuit, said second set of input/output pins being coupled to a plurality of data storage devices on said integrated circuits on said integrated circuit;    said second set of test contacts on said tester containing a number of contacts less in number than said second set of sockets on said board;    wiring on said data interface board for coupling a respective one of said test contacts in said first set of test contacts to a respective socket in said first set of sockets and for coupling a respective one of said test contacts in said second set of test contacts in parallel to a plurality of respective sockets in said second set of sockets.    
   
   
       2 . A test apparatus for testing an integrated circuit that has a scan-based interface by which data can be shifted through a chain of clock storage devices and extracted sequentially therefrom to test the device data storage device's input/output (I/O) signal pins for alternating current (AC) defects comprising: 
 a tester having first and second sets of tester contacts; and    an integrated circuit having a set of functional circuits and a plurality of clocked data storage devices;    first means for coupling each of said functional circuits to a respective tester contact said first set of tester contacts; and    second means for coupling each respective tester contact in said second set of tester contacts to a plurality of said clocked data storage devices.    
   
   
       3 . The test apparatus of  claim 1  wherein said first and second means comprises wiring on a printed circuit board.  
   
   
       4 . A method of testing the input/output pins of an integrated circuit for alternating current (AC) defects consisting of the steps of: 
 selecting an integrated circuit having a plurality of functional circuits coupled to a first set of input/output pins and a plurality of clocked storage devices arranged in data storage chains coupled to a second set of input/output pins and a scan-based interface by which data can be shifted through said chains of said clocked storage devices and extracted sequentially therefrom;    coupling a tester having a first set and a second set of tester contacts to said integrated circuit;    coupling said first set of tester contacts to said functional circuits through said first set of input/output pins;    coupling respective ones of said second set of tester contacts to respective chains of said clocked storage devices;    scanning a series of clock pulses into each of said clocked storage devices;    scanning a data stream comprised of data bits into a first one of said chains to drive the input/output pins connected to said first one of said chains to a low state and then to a high state by determining the amount of time it takes for the pin to shift from a low state to a high state and then back to the low state, after the clock pulse that causes the transition has been received.    
   
   
       5 . The method of  claim 4  wherein said data stream comprises: 
 (Trailing edge of data) 000 . . . . 0101110 . . . 000 (Leading edge of data).    
   
   
       6 . A semiconductor test apparatus for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects comprising; 
 a tester having a first and second sets of test contacts thereon;    an integrated circuit having a plurality of data storage latches and a circuit block containing selected functional circuits coupled to said data storage latches;    said first set of test contacts containing a number of contacts which is less than the number of said data storage devices;    each respective test contact in said first set of test contacts being coupled, in parallel to a plurality of the input/output pins of said data storage latches; and    each respective test contact of second set of test contacts being coupled to the functional circuit block on said integrated circuit.