Information processing apparatus

Abstract

A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

1 . An information processing apparatus comprising a CPU, a memory and a prefetch means for prefetching a series of instructions including a predetermined number of instructions and data before said CPU executes any of the instructions or data in said series of instructions, further comprising: 
 a prefetch address calculation means for prefetching an interruption vector table when an interruption request arises, extracting the head address of an interruption routine out of read data in said interruption vector table and prefetching said head address.    
     
     
         2 . The information processing apparatus according to  claim 1 , wherein said prefetch address calculation means performs a transition to a state of outputting the address of said interruption vector table in response to the assertion of an interruption and performs a transition to a state of outputting the head address of said interruption routine out of said read data in response to the assertion of a signal indicating the validity of read data for storing the interruption vector table read from said memory.  
     
     
         3 . An information processing apparatus comprising a CPU, a memory and a prefetch means for prefetching a series of instructions including a predetermined number of instructions and data before said CPU executes any of the instructions or data in said series of instructions, further comprising: 
 a prefetch address calculation means for detecting a prescribed “return from exception” (RTE) instruction or “return from subroutine” (RTS) instruction contained in said series of instructions at the time when said series of instructions is stored into a prefetch buffer and prefetching target instructions of RTE and RTS.    
     
     
         4 . The information processing apparatus according to  claim 3 , wherein 
 said prefetch address calculation means holds the address of said target instructions of RTF and RTS outputted from said CPU before branching into a interruption routine or a subroutine and, when said prescribed RTF interruption or RTS instruction contained in the series of instructions of said prefetch buffer has been detected, outputs said address of said target instructions of RTF and RTS held by said prefetch address calculation means.    
     
     
         5 . An information processing apparatus comprising a CPU, a memory and a prefetch means for prefetching a series of instructions including a predetermined number of instructions and data before said CPU executes any of the instructions or data in said series of instructions, further comprising: 
 a prefetch address calculation means for prefetching a branch target address by decoding at least one information for calculation of branch target address and a series of instructions for branch including branch instructions, from a current instruction buffer storing said series of instructions currently accessed with said CPU.    
     
     
         6 . The information processing apparatus according to  claim 5 , wherein 
 said prefetch address calculation means outputs a prefecth request of a target branch and calculates said target address for branch, on condition that said series of instructions for branch meet a specific order of instructions and the register indexes of the objects of all instructions contained in said series of instructions for branch coincide together.    
     
     
         7 . An information processing apparatus comprising a CPU, a memory and a prefetch means for prefetching a series of instructions including a predetermined number of instructions and data before said CPU executes any of the instructions or data in said series of instructions, further comprising: 
 a prefetch address calculation means for prefetching a branch target address by decoding at least one information for calculation of branch target address and a series of instructions for branch including branch instructions, from a current instruction buffer storing a series of instructions currently accessed with said CPU and a previous instruction buffer storing a series of instructions previously accessed with said CPU.    
     
     
         8 . The information processing apparatus according to  claim 7 , wherein 
 when a series of instructions stored in said previous instruction buffer and a series of instructions stored in said current instruction buffer are consecutive, said prefetch address calculation means decodes a series of instruction for branch instruction spanning said previous instruction buffer and said current instruction buffer.    
     
     
         9 . An information processing apparatus comprising a CPU, a memory and a prefetch means for prefetching a series of instructions including a predetermined number of instructions and data before said CPU executes any of the instructions or data in said series of instructions, further comprising: 
 at least one RTS buffer for storing a series of target instructions of RTS, and a current instruction buffer for storing a series of instructions currently accessed by said CPU, wherein    said series of instructions in said current instruction buffer are stored into said RTS buffer.    
     
     
         10 . The information processing apparatus according to  claim 9 , further comprising: 
 an update pointer of RTF buffer for selecting, when at least two of said RTS buffers exist, the RTS buffer to be updated out of them, wherein said plurality of RTF buffers have validity bits indicating the validity or invalidity of the entry to be stored (1: valid, 0: invalid), and hit bits indicating whether or not the entry to be stored is hit (1: hit, 0: not hit), and said update pointer of RTF buffer is calculated from said validity bit and said hit bit.    
     
     
         11 . The information processing apparatus according to  claim 10 , wherein 
 the calculation of said update pointer selects the RTF buffer in which the hit bit is 1, or when the RTF buffer in which said hit bit is 1 does not exist, it selects the RTF buffer in which the stored entry is invalid.    
     
     
         12 . The information processing apparatus according to  claim 5 , wherein 
 in case of simultaneous occurrence of a prefetch request from said prefetch address calculation means and a read request from said CPU, priority is given to said read request from the CPU.    
     
     
         13 . The information processing apparatus according to  claim 9 , wherein 
 storing of any series of instructions in said current instruction buffer to said RTS buffer is performed when a branch instruction to a subroutine is detected out of the first through last but one series of instructions in said current instruction buffer.