Polish pad to change polish rate on wafer by adjusting groove width and density

Abstract

The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.

1 .- 53 . (canceled)  
     
     
         54 . A polish pad comprising: 
 a first set of grooves disposed in a first area, said first set of grooves having a first width; and    a second set of grooves disposed in a second area, said second set of grooves having a second width, wherein said first set of grooves does not intersect said second set of grooves and wherein said first width is smaller than said second width to reduce polish rate in said first area.    
     
     
         55 . The polish pad of  claim 54  wherein said first area corresponds to low points of a wafer to be polished by said polish pad.  
     
     
         56 . The polish pad of  claim 55  wherein center of said wafer is only polished by center of said polish pad.  
     
     
         57 . The polish pad of  claim 54  wherein said second area corresponds to high points of a wafer to be polished by said polish pad.  
     
     
         58 . The polish pad of  claim 57  wherein center of said wafer is only polished by center of said polish pad.  
     
     
         59 . A polish pad comprising: 
 a first set of grooves disposed in a first area, said first set of grooves having a first density; and    a second set of grooves disposed in a second area, said second set of grooves having a second density, wherein said first set of grooves does not intersect said second set of grooves and wherein said first density is smaller than said second density to reduce polish rate in said first area.    
     
     
         60 . The polish pad of  claim 59  wherein said first area corresponds to low points of a wafer to be polished by said polish pad.  
     
     
         61 . The polish pad of  claim 60  wherein center of said wafer is only polished by center of said polish pad.  
     
     
         62 . The polish pad of  claim 59  wherein said second area corresponds to high points of a wafer to be polished by said polish pad.  
     
     
         63 . The polish pad of  claim 62  wherein center of said wafer is only polished by center of said polish pad.