Method for making high performance semiconductor memory devices

Abstract

High performance memory devices have been realized by applying an Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit-line-write mechanism allows us to reduce the number of bit lines by 50% for static memory devices. The resulting memory device can be as fast as registers files while its area is smaller than prior art high-density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuits in future IC manufacture technologies.

1 . A method for performing data access to a semiconductor memory array having a plurality of memory cells comprising: 
 connecting a bit-line and a word-line to each of the memory cells;    providing a memory cell read/write voltage control means for controlling the bit-line to have at least three bitline voltage ranges between a power supply voltage and a ground voltage for the memory array to carry out said data access through the bit-line and the word-line.    
   
   
       2 . The method of  claim 1  further comprising a step of: 
 configuring each of the memory cells as five-transistors (5T) static random access memory (SRAM) cell with one of said five transistors functioning as a pass-transistor connected to a single wordline and a single bitline for carrying out said data access through said single bitline and said single wordline.    
   
   
       3 . The method of  claim 1  further comprising a step of: 
 configuring each of the memory cells as six-transistors (6T) static random access memory (SRAM) cell with two of said five transistors functioning as a pass-transistors connected to a first and second wordlines and a first and second bitlines for carrying out said data access through said first and second bitlines and said first and second wordlines as a dual-port data-access memory array.