Novel EEPROM cell structure and array architecture

Abstract

An EEPROM cell device on a substrate is achieved. The device comprises, first, a selection transistor having gate, drain, source, and channel. The drain is defined as a cell bit line. An isolation transistor has gate, drain, source, and channel. The source is defined as a cell source line. Finally, a floating gate transistor has control gate, floating gate, drain, source, and channel. The drains and sources of each transistor comprise a diffusion layer in the substrate. The channels of each transistor comprise the substrate. The floating gate transistor drain is coupled to the selection transistor source. The floating gate transistor source is coupled to the isolation transistor drain. The device is programmed and erased by charge tunneling between the floating gate and the floating gate transistor channel. The device may further comprise an isolation well underlying the diffusion layer. A two transistor EEPROM cell is disclosed. Several array architectures using the EEPROM cell are disclosed.

1 - 5 . (canceled)  
   
   
       6 . A method to erase an EEPROM cell device, said method comprising: 
 forcing said substrate to ground;    turning OFF said selection transistor to isolate said floating gate transistor from said cell bit line;    turning OFF said isolation transistor to isolate said floating gate transistor from said cell source line; and    forcing said floating gate transistor control gate to a tunneling voltage to cause tunneling between said floating gate and said floating gate transistor channel and wherein said EEPROM cell device comprises:    a selection transistor having gate, drain source, and channel, wherein said drain is defined as a cell bit line;    an isolation transistor having gate, drain, source, and channel, wherein said source is defined as a cell source line; and    a floating gate transistor having control gate, floating gate, drain, source, and channel, wherein said drains and sources of each said transistor comprise a diffusion layer in said substrate, wherein said channels of each said transistor comprise said substrate, wherein said floating gate transistor drain is coupled to said selection transistor source, wherein said floating gate transistor source is coupled to said isolation transistor drain, and wherein said device is programmed and erased by charge tunneling between said floating gate and said floating gate transistor channel.    
   
   
       7 . The device according to  claim 6  wherein said device is programmed by a method comprising: 
 forcing said substrate to ground;    forcing said cell bit line to ground; turning ON said selection transistor to couple said cell bit line to said floating gate transistor drain;    turning OFF said isolation transistor to isolate said floating gate transistor source from said cell source line; and    forcing said floating gate transistor control gate to a tunneling voltage to cause tunneling between said floating gate and said floating gate transistor channel.    
   
   
       8 . The device according to  claim 6  wherein said device is inhibited from programming by a method comprising: 
 forcing said substrate to ground;    forcing said cell bit line to an inhibit voltage;    turning ON said selection transistor to couple said cell bit line to said floating gate transistor drain;    turning OFF said isolation transistor to isolate said floating gate transistor source from said cell source line; and    forcing said floating gate transistor control gate to a tunneling voltage wherein said inhibit voltage on said floating gate drain prevents tunneling between said floating gate and said floating gate transistor channel.    
   
   
       9 - 13 . (canceled)  
   
   
       14 . A method to program and to erase an EEPROM cell device, said method comprising: 
 forcing said substrate to ground;    forcing said cell bit line to ground;    turning OFF said isolation transistor to isolate said floating gate transistor from said cell source line; and    forcing said floating gate transistor control gate to a tunneling voltage to cause tunneling between said floating gate and said floating gate transistor channel wherein said EEPROM cell device comprises:    an isolation transistor having gate, drain, source, and channel, wherein said source is defined as 15 a cell source line; and    a floating gate transistor having control gate, floating gate, drain, source, and channel, wherein said drains and sources of each said transistor comprise a diffusion layer in said substrate, wherein said channels of each said transistor comprises said substrate, wherein said floating gate transistor drain is defined as a cell bit line, wherein said floating gate transistor source is coupled to said isolation transistor drain, and wherein said device is programmed and erased by charge tunneling between said floating gate and said floating gate transistor channel.    
   
   
       15 . The device according to  claim 14  wherein said device is inhibited from programming by a method comprising: 
 forcing said substrate to ground;    forcing said cell bit line to an inhibit voltage;    turning OFF said isolation transitor to isolate said floating gate transistor source from said cell source line; and    forcing said floating gate transistor control gate to a tunneling voltage wherein said inhibit voltage on said floating gate drain prevents tunneling between said floating gate and said floating gate transistor channel.    
   
   
       16 . An EEPROM array device on a substrate, said device comprising a plurality of bytes, each said byte further comprising: 
 a plurality of cells, each said cell comprising:    a selection transistor having gate, drain, source, and channel, wherein said drain is defined as a cell bit line and wherein said gate is coupled to said gate of all said cells in said byte to form a byte selection gate line;    an isolation transistor having gate, drain, source, and channel, wherein said source is defined as a cell source line, wherein said cell source line is coupled to said cell source line of all said cells in said byte to form a byte source line, and wherein said gate is coupled to said gate of all said cells in said byte to form a byte isolation gate line; and    a floating gate transistor having control gate, floating gate, drain, source, and channel, wherein said drains and sources of each said transistor comprise a diffusion layer in said substrate, wherein said channels of each said transistor comprise said substrate, wherein said floating gate transistor drain is coupled to said selection transistor source, wherein said floating gate transistor source is coupled to said isolation transistor drain, wherein said device is programmed and erased by charge tunneling between said floating gate and said floating gate transistor channel, and wherein said control gate is coupled to said control gate of all said cells of said byte to form a byte wordline; and    a wordline transistor having gate, drain, source, and channel, wherein said gate is coupled to a y selection line, wherein said source is coupled to an x selection line, wherein said drain is coupled to said byte wordline, and wherein said channel is coupled to a well voltage line to prevent forward bias of said drain and source to said channel.    
   
   
       17 . The device according to  claim 16  wherein said diffusion layer comprises an n-type doping and said substrate comprises a p-type doping.  
   
   
       18 . The device according to  claim 16  wherein said diffusion layer comprises a buried n-type doping and said substrate comprises a p-type doping.  
   
   
       19 . The device according to  claim 16  wherein said diffusion layer comprises a p-type doping and said substrate comprises an n-type doping.  
   
   
       20 . The device according to  claim 16  further comprising an isolating well underlying said diffusion layer.  
   
   
       21 . The device according to  claim 16  wherein said wordline transistor comprises a PMOS transistor in an isolating well region in said substrate.  
   
   
       22 . The device according to  claim 16  wherein said wordline transistor comprises an NMOS transistor in an isolating well region in said substrate.  
   
   
       23 . The device according to  claim 16  wherein a selected said byte is erased by a method comprising: 
 forcing said substrate to ground;    turning OFF said selection transistors of said selected byte to thereby isolate said floating gate transistors from said cell bit lines;    turning OFF said isolation transistors of said selected byte to thereby isolate said floating gate transistors from said byte source line;    forcing said x selection line of said selected byte to a tunneling voltage; and    turning ON said byte wordline transistor of said selected byte to force said byte wordline to said tunneling voltage and to thereby cause tunneling between said floating gates and said floating gate transistor channels.    
   
   
       24 . The device according to  claim 16  wherein a selected cell of a selected said byte is programmed while an unselected cell of said selected byte is inhibited from programming by a method comprising: 
 forcing said substrate to ground;    turning ON said selection transistors of said selected byte cell to thereby couple said floating gate transistors to said cell bit lines;    turning OFF said isolation transistors of said selected byte to thereby isolate said floating gate transistors from said byte source line;    forcing said x selection line to a tunneling voltage;    forcing said cell bit line of said selected cell to ground;    forcing said cell bit line of said unselected cell to an inhibit voltage; and    turning ON said wordline transistor of said selected byte to force said byte wordline to said tunneling voltage and to thereby cause tunneling between said selected cell floating gate and said selected cell floating gate transistor channel wherein the presence of said inhibit voltage prevents said tunneling in said unselected cell.    
   
   
       25 . The device according to  claim 16  wherein said byte further comprises a compliment wordline transistor having gate, drain, source, and channel, 
 wherein said gate is coupled to a compliment y selection line,    wherein said drain is coupled to a compliment x selection line, wherein said source is coupled to said byte wordline, and    wherein said channel is coupled to said well voltage line to prevent forward bias of said drain and source to said channel.    
   
   
       26 . The device according to  claim 25  wherein said wordline transistor and said compliment wordline transistor comprise PMOS transistors in an isolating well region in said substrate.  
   
   
       27 . The device according to  claim 25  wherein said wordline transistor and said compliment wordline transistor comprise NMOS transistors in an isolating well region in said substrate.  
   
   
       28 . The device according to  claim 25  wherein a selected said byte is erased by a method comprising: 
 forcing said substrate to ground;    turning OFF said selection transistors of said selected byte to thereby isolate said floating gate transistors from said cell bit lines;    turning OFF said isolation transistors of said selected byte to thereby isolate said floating gate transistors from said byte source line;    forcing said x selection line of said selected byte to a tunneling voltage;    forcing said compliment x selection line of selected byte to ground;    turning OFF said byte compliment wordline transistor of said selected byte to isolate said selected wordline from said compliment x selection line; and    turning ON said byte wordline transistor of said selected byte to force said byte wordline to said tunneling voltage and to thereby cause tunneling between said floating gates and said floating gate transistor channels.    
   
   
       29 . The device according to  claim 25  wherein a selected cell of a selected said byte is programmed while an unselected cell of said selected byte is inhibited from programming by a method comprising: 
 forcing said substrate to ground;    turning ON said selection transistors of said selected byte  1  to thereby couple said floating gate transistors to said cell bit lines;    turning OFF said isolation transistors of said selected byte to thereby isolate said floating gate transistors from said byte source line;    forcing said x selection line to a tunneling voltage;    forcing said compliment x selection line to ground;    forcing said cell bit line of said selected cell to ground;    forcing said cell bit line of said unselected cell to an inhibit voltage;    turning OFF said compliment wordline transistor of said selected byte to isolate said byte wordline from said compliment x selection line; and    turning ON said wordline transistor of said selected byte to force said byte wordline to said tunneling voltage and to thereby cause tunneling between said selected cell floating gate and said selected cell floating gate transistor channel wherein the presence of said inhibit voltage prevents said tunneling on said unselected cells.    
   
   
       30 . An EEPROM array device on a substrate, said device comprising a plurality of bytes, each said byte further comprising: 
 a plurality of cells, each said cell comprising:    an isolation transistor having gate, drain, source, and channel, wherein said source is defined as a cell source line, wherein said cell source line is coupled to said cell source line of all said cells in said byte to form a byte source line, and wherein said gate is coupled to said gate of all said cells in said byte to form a byte isolation gate line; and    a floating gate transistor having control gate, floating gate, drain, source, and channel, wherein said drains and sources of each said transistor comprise a diffusion layer in said substrate, wherein said channels of each said transistor comprise said substrate, wherein said floating gate transistor drain forms a cell bit line, wherein said floating gate transistor source is coupled to said isolation transistor drain, wherein said device is programmed and erased by charge tunneling between said floating gate and said floating gate transistor channel, and wherein said control gate is coupled to said control gate of all said cells of said byte to form a byte wordline;    a wordline transistor having gate, drain, source, and channel, wherein said gate is coupled to a y selection line, wherein said source is coupled to an x selection line, wherein said drain is coupled to said byte wordline, and wherein said channel is coupled to a well voltage line to prevent forward bias of said drain and source to said channel; and    a compliment wordline transistor having gate, drain, source, and channel, wherein said gate is coupled to a compliment y selection line, wherein said drain is coupled to a compliment x selection line, wherein said source is coupled to said byte wordline, and wherein said channel is coupled to said well voltage line to prevent forward bias of said drain and source to said channel.    
   
   
       31 . The device according to  claim 30  wherein said diffusion layer comprises an n-type doping and said substrate comprises a p-type doping.  
   
   
       32 . The device according to  claim 30  wherein said diffusion layer comprises a buried n-type doping and said substrate comprises a p-type doping.  
   
   
       33 . The device according to  claim 30  wherein said diffusion layer comprises a p-type doping and said substrate comprises an n-type doping.  
   
   
       34 . The device according to  claim 30  further comprising an isolating well underlying said diffusion layer.  
   
   
       35 . The device according to  claim 30  wherein said wordline transistor and said compliment wordline transistor comprise PMOS transistors in an isolating well region in said substrate.  
   
   
       36 . The device according to  claim 30  wherein said wordline transistor and said compliment wordline transistor comprise NMOS transistors in an isolating well region in said substrate.  
   
   
       37 . The device according to  claim 30  wherein a selected said byte is erased by a method comprising: 
 forcing said substrate to ground;    turning OFF said isolation transistors of said selected byte to thereby isolate said floating gate transistors from said byte source line;    forcing said x selection line of said selected byte to a tunneling voltage;    forcing said compliment x selection line of said selected byte to ground;    turning OFF said byte compliment wordline transistor of said selected byte to isolate said byte wordline from said compliment x selection line; and    turning ON said byte wordline transistor of said selected byte to force said byte wordline to said tunneling voltage and to thereby cause tunneling between said floating gates and said floating gate transistor channels.    
   
   
       38 . The device according to  claim 30  wherein a selected cell of a selected said byte is programmed while an unselected cell of said selected byte is inhibited from programming by a method comprising: 
 forcing said substrate to ground;    turning OFF said isolation transistors of said selected byte to thereby isolate said floating gate transistors from said byte source line;    forcing said x selection line to a tunneling voltage;    forcing said compliment x selection line to ground;    forcing said cell bit line of said selected cell to ground;    forcing said cell bit line for said unselected cell to an inhibit voltage;    turning OFF said compliment wordline transistor of said selected byte to isolate said byte wordline from said compliment x selection line; and    turning ON said wordline transistor of said selected byte to force said byte wordline to said tunneling voltage and to thereby cause tunneling between said selected cell floating gate and said selected cell floating gate transistor channel wherein the presence of said inhibit voltage prevents said tunneling in said unselected cell.    
   
   
       39 . The device according to  claim 30  further comprising a plurality of sub-bit line transistors wherein each said sub-bit line transistor is coupled between each said cell bit line and an array bit line to thereby reduce the number of said floating gate transistors exposed to a tunneling voltage during erasing and programming.