Method of manufacturing a semiconductor device having a protection circuit

Abstract

The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.

1 . Manufacturing method of a semiconductor device, comprising the step of forming an internal circuit including a plurality of transistor groups each having a gate dielectric layer of an independently set film thickness on a substrate, wherein one of said transistors is formed as a power source protection element during said step of forming said internal circuit without performing an additional process.  
     
     
         2 . The manufacturing method as set forth in  claim 1 , wherein one of said transistors that has the thinnest gate dielectric layer is formed as the power source protection element.  
     
     
         3 . The manufacturing method as set forth in  claim 1 , wherein said step of forming said internal circuit includes forming gate dielectric layers of said power source protection element and at least one of said transistors at a same time; and a channel dosage for said power source protection element is more than a channel dosage for said at least one of said transistors.  
     
     
         4 . The manufacturing method as set forth in  claim 2 , wherein said step of forming said internal circuit includes forming gate dielectric layers of said power source protection element and at least one of said transistors at a same time; and a channel dosage for said power source protection element is more than a channel dosage for said at least one of said transistors.  
     
     
         5 . The manufacturing method as set forth in  claim 1 , wherein said channel dosage for said power source protection element is equal to a total channel dosage for at least two of said transistors included in said internal circuit.  
     
     
         6 . The manufacturing method as set forth in  claim 2 , wherein said channel dosage for said power source protection element is equal to a total channel dosage for at least two of said transistors included in said internal circuit.  
     
     
         7 . The manufacturing method as set forth in  claim 1 , wherein said step of forming said internal circuit includes: 
 performing a first impurity ion implantation into a first forming region of a first transistor other than said power source protection element included in said transistors; and    performing a second impurity ion implantation into a second forming region of a second transistor other than said power source protection element or said first transistor included in said transistors;    wherein said first impurity ion implantation and said second impurity ion implantation are performed into a region of said power source protection element for adjusting a threshold voltage of said power source protection element.    
     
     
         8 . The manufacturing method as set forth in  claim 2 , wherein said step of forming said internal circuit includes: 
 performing a first impurity ion implantation into a first forming region of a first transistor other than said power source protection element included in said transistors; and    performing a second impurity ion implantation into a second forming region of a second transistor other than said power source protection element or said first transistor included in said transistors;    wherein said first impurity ion implantation and said second impurity ion implantation are performed into a region of said power source protection element for adjusting a threshold voltage of said power source protection element.