Insulated gate bipolar transistor and electrostatic discharge cell protection utilizing insulated gate bipolar tansistors

Abstract

IGBTs and circuits can be designed to improve the ability of circuits and systems to withstand ESD events. In addition pads can be designed to take advantage of the circuits and IGBTs to withstand and dissipate ESD events.

1 . An insulated gate bipolar transistor comprising: 
 a substrate;    a first well region within the substrate;    a collector region within the first well region;    a second well region within the substrate;    an first emitter region within the second well region;    a second emitter region within the second well region; and    a first electrode connected with the first well region and the collector region.    
   
   
       2 . The insulated gate bipolar transistor of  claim 1  wherein the insulated gate bipolar transistor comprises a lateral insulated gate bipolar transistor.  
   
   
       3 . The insulated gate bipolar transistor of  claim 2  wherein the insulated gate bipolar transistor comprises an isolation region located between the substrate and the first well region.  
   
   
       4 . The insulated gate bipolar transistor of  claim 2  further comprising a punch through reduction region located substantially adjacent to the collector region.  
   
   
       5 . The insulated gate bipolar transistor of  claim 4  wherein the punch through reduction region is approximately two microns in width.  
   
   
       6 . The insulated gate bipolar transistor of  claim 2  further comprising a buffer region within the first well, the buffer region abutting the collector region.  
   
   
       7 . The insulated gate bipolar transistor of  claim 1  wherein the insulated gate bipolar transistor comprises a vertical gate bipolar transistor.  
   
   
       8 . An insulated gate bipolar transistor comprising: 
 a substrate;    a first well region within the substrate;    a first collector region within the first well region;    a second collector region with the first well region;    a second well region within the substrate;    an first emitter region within the second well region; and    a second emitter region within the second well region.    
   
   
       9 . The insulated gate bipolar transistor of  claim 8  wherein the insulated gate bipolar transistor comprises a lateral insulated gate bipolar transistor.  
   
   
       10 . The insulated gate bipolar transistor of  claim 9  wherein the lateral insulated gate bipolar transistor comprises an isolation region located between the substrate and first well region.  
   
   
       11 . The insulated gate bipolar transistor of  claim 9  wherein the lateral insulated gate bipolar transistor comprises a third well region within the first well region.  
   
   
       12 . The insulated gate bipolar transistor of  claim 9  wherein the lateral insulated gate bipolar transistor comprises an isolation region located between the substrate and second well region.  
   
   
       13 . The insulated gate bipolar transistor of  claim 9  further comprising a punch through reduction region located substantially adjacent to the collector region.  
   
   
       14 . The insulated gate bipolar transistor of  claim 13  wherein the punch through reduction region is approximately 2 microns in width.  
   
   
       15 . The insulated gate bipolar transistor of  claim 9  further comprising a buffer region within the first well, the buffer region abutting the first collector region.  
   
   
       16 . The insulated gate bipolar transistor of  claim 8  wherein the insulated gate bipolar transistor comprises a vertical insulated gate bipolar transistor.  
   
   
       17 . An insulated gate bipolar transistor comprising: 
 a substrate;    a first well region within the substrate;    a collector region within the first well region;    a second well region within the substrate;    an first emitter region within the second well region;    a second emitter region within the second well region; and    a third well region within the first well region.    
   
   
       18 . The insulated gate bipolar transistor of  claim 17  wherein the insulated gate bipolar transistor comprises a lateral insulated gate bipolar transistor.  
   
   
       19 . The insulated gate bipolar transistor of  claim 18  wherein the lateral insulated gate bipolar transistor comprises an isolation region located between the substrate and first well region.  
   
   
       20 . The insulated gate bipolar transistor of  claim 18  wherein the lateral insulated gate bipolar transistor comprises another collector region within the first well region.  
   
   
       21 . The insulated gate bipolar transistor of  claim 18  wherein the lateral insulated gate bipolar transistor comprises an isolation region located between the substrate and second well region.  
   
   
       22 . The insulated gate bipolar transistor of  claim 18  further comprising a punch through reduction region located substantially adjacent to the collector region.  
   
   
       23 . The insulated gate bipolar transistor of  claim 22  wherein the punch through reduction region is approximately 2 microns in width.  
   
   
       24 . The insulated gate bipolar transistor of  claim 18  wherein the insulated gate bipolar transistor comprises a vertical gate bipolar transistor.  
   
   
       25 . The insulated gate bipolar transistor of  claim 18  further comprising a buffer region within the first well, the buffer region abutting the collector region.