Soft-landing etching method using doping level control

Abstract

The method of the present invention comprises the steps of: (a) laying on a prior layer, a first oxide layer doped in one form; (b) laying on said first oxide layer, a second oxide layer doped in a different form; (c) patterning said layers; (d) etching the second layer with an etchant having high selectivity to said second doped oxide layer; and (e) etching the first layer with an etchant having high selectivity to said first doped oxide layer. As the etch rate is higher for the highly doped oxide than that for the lightly doped oxide, high selectivity of etching between such layers can therefore be attained. A lightly doped silicon oxide layer may therefore be used to stop etching at an optimal thickness over the complicated layer of substrate. The lightly doped silicon oxide area may be covered with a layer of highly doped silicon oxide layer which may be etched with a specific etchant.

1 . A method of fabricating a semiconductor device comprising the steps of: 
 (a) laying on a prior layer, a first oxide layer doped in one form;    (b) laying on the first oxide layer, a second oxide layer doped in a different form;    (c) patterning the first oxide layer and second oxide layer;    (d) etching the second oxide layer with a second etchant, wherein the second etchant has a high selectivity to the second oxide layer, and wherein the second etchant etches a region of second oxide layer to expose the first oxide layer; and    (e) etching the exposed region of the first oxide layer relative to the etched region of second layer with a first etchant, wherein the first etchant has a high selectivity to the first oxide layer, wherein the first etchant etches a region of first oxide layer to expose the prior layer, and wherein the first etchant does not over-etch and damage the prior layer.    
   
   
       2 . The method according to  claim 1 , wherein the first oxide layer is lightly doped and the second oxide layer is highly doped.  
   
   
       3 . The method according to  claim 2 , wherein the first and second oxide layers are respectively doped with different concentration of dopants.  
   
   
       4 . The method according to  claim 2 , wherein the first and second oxide layers are respectively doped with different doping materials.  
   
   
       5 . The method according to  claim 1 , wherein the first and second etchants are respectively selective to the first and second oxide layers.  
   
   
       6 . The method according to  claim 1 , wherein step (e) further comprises etching the exposed region of the first oxide layer relative to the etched region of second layer with a third etchant, wherein the third etchant has a low selectivity to the first oxide layer, wherein the third etchant etches a region of first oxide layer to expose the prior layer, and wherein the third etchant does not over-etch and damage the prior layer.  
   
   
       7 . The method according to  claim 1 , wherein the first and second oxide layers are doped with at least one element from boron (B), phosphorus (P) and arsenic (As) by ion implantation.  
   
   
       8 . The method according to  claim 2 , wherein the lightly doped oxide layer is one of borophosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), USG, NSG.  
   
   
       9 . The method according to  claim 2 , wherein the thickness of the lightly doped oxide layer ranges from 50 to 500 Å.  
   
   
       10 . The method according to  claim 2 , wherein the lightly doped oxide layer is heated at high temperature to obtain higher selectivity.  
   
   
       11 . The method according to  claim 1 , wherein the etching may be performed in more than two etching steps (d) and (e) according to the etching selectivity which is suitable for the semiconductor device's fabrication process.  
   
   
       12 . The method according to  claim 1 , wherein the etching steps (d) and (e) are performed in an appropriate etch process chamber to achieve an anisotropic etch, wherein the anisotropic etch creates a contact hole.  
   
   
       13 . The method according to  claim 13 , wherein the etching is carried out in a gas mixture comprising 2 or more gases in combination of the following: 
 CF 4 , C 4 F 6 , CH 2 F 2  with O 2 , N 2 , CO, CHF 3 .    
   
   
       14 . A semiconductor wafer processed with a method according to  claim 1 .  
   
   
       15 . A semiconductor device fabricated according to a method according to  claim 1.