Non-volatile memory devices and methods of fabricating the same

Abstract

Non-volatile memory devices and fabrication methods thereof are provided. The device includes a plurality of isolation layers formed at a semiconductor device, a plurality of stacked gates crossing over an active region between the isolation layers, and an oxidation barrier layer covering the stacked gate. Each of the stacked gates has a control gate electrode crossing over the active region, a floating gate interposed between the control gate electrode and the active region, and an inter-gate dielectric layer interposed between the control gate electrode and the floating gate. Also, the inter-gate dielectric layer has a bottom dielectric layer, an intermediate dielectric layer and a top dielectric layer which are sequentially stacked. The oxidation barrier layer is formed prior to a subsequent thermal oxidation process for curing etch damage that occurs during formation of the stacked gates.

1 . A method of fabricating a non-volatile memory device, comprising: 
 forming a plurality of isolation layers at a semiconductor substrate to define an active region;    forming a floating gate pattern covering the active region;    sequentially forming an inter-gate dielectric layer and a control gate conductive layer on the substrate having the floating gate pattern;    successively patterning the control gate conductive layer, the inter-gate dielectric layer and the floating gate pattern to form a plurality of stacked gates crossing over the active region;    forming a conformal oxidation barrier layer on the entire surface of the resultant structure where the stacked gates are formed; and    performing a thermal oxidation process to cure etch damage that occurs during formation of the stacked gates.    
   
   
       2 . The method of  claim 1 , wherein the control gate conductive layer is formed of a polysilicon layer or a metal polycide layer.  
   
   
       3 . The method of  claim 1 , wherein the oxidation barrier layer is formed of a CVD oxide layer.  
   
   
       4 . The method of  claim 1 , wherein the oxidation barrier layer is formed to a thickness of 50 angstroms and 100 angstroms.  
   
   
       5 . The method of  claim 1 , wherein performing the thermal oxidation process is followed by forming source/drain regions at the active region between the stacked gates.