Mirror image non-volatile memory cell transistor pairs with single poly layer

Abstract

An arrangement of non-volatile memory transistors constructed in symmetric pairs within the space defined by intersecting pairs of word and bit lines of a memory array. The transistors have spaced apart sources and drains separated by a channel and having a floating gate over the channel characteristic of electrically erasable programmable read only memory transistors, except that there is no second poly gate. Only a single poly gate is used as a floating charge storage gate. This floating gate is placed sufficiently close to the source or drain of the device as to enable band-to-band tunneling. The floating gate is extended over the substrate to cross a word line where the floating gate is in a capacitive relation. The word line is used to program and erase the floating gate in combination with a source or drain electrode. A block erase mode is available so that the arrangement of transistors can operate as a flash memory. The single layer of poly has a T-shape, with the T-top used as the communication member with the word line and a T-base used as a floating gate. Both T-members are at the same potential. The intersecting pairs of word and bit lines resemble a tic-tac-toe pattern, with a central clear zone wherein pairs of symmetric non-volatile memory transistors are built.

1 . A method of making a memory storage device in a semiconductor substrate for a non-volatile memory array comprising, 
 establishing spaced apart parallel word lines running in a first direction within the substrate,    establishing spaced apart parallel bit lines running in a second direction within the substrate orthogonal to the first direction and intersecting the word lines, forming a tic-tac-toe pattern having a central zone,    forming a mirror-image MOS charge store transistor pair within the central zone, each transistor having a first electrode communicating with a bit line and a second electrode communicating with a word line.    
   
   
       2 . This method of  claim 1  further defined by forming said paid of mirror-image transistors across an imaginary line parallel to the word lines.  
   
   
       3 . The method of  claim 2  further defined wherein said imaginary line is midway between the word lines.  
   
   
       4 . The method of  claim 2  further defined by forming each transistor of said pair with the electrodes having a cross-section parallel to said imaginary line.  
   
   
       5 . The method of  claim 1  further defined by forming each transistor with only a single layer of poly.  
   
   
       6 . The method of  claim 5  further defined by spacing said layer of poly in a capacitive relation to the substrate.  
   
   
       7 . The method of  claim 6  further defined by spacing said layer of poly in a relation to said electrodes to induce band-to-band tunneling.  
   
   
       8 . The method of  claim 1  further defined by applying voltage to the bit lines in phases within a clock cycle.  
   
   
       9 . The method of  claim 1  further defined by making a memory array having rows and columns of mirror-image MOS storage transistor pairs within tic-tac-toe patterns formed by intersecting pairs of word and bit lines.