Low volt/high volt transistor

Abstract

A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in only the high-voltage transistor prior to conducting an oxidation process to protect the substrate and gate electrode. After the oxidation process is performed, the low-voltage transistor is subjected to an LDD implantation process. The resultant semiconductor device provides a high-voltage transistor having a deeper LDD region junction depth than the low-voltage transistor, ensuring reliability and performance.

1 . A method of manufacturing a semiconductor device, comprising: 
 providing a substrate;    forming a gate electrode over a substrate;    forming at least two transistors having different operation voltages over the substrate;    performing a LDD implantation into the transistor having a higher operation voltage;    performing an oxidation process on the transistors; and    performing a LDD implantation into the transistor having a lower operation voltage.    
   
   
       2 . The method of  claim 1 , wherein each transistor includes a gate insulating film, source/drain regions and a channel located directly under the gate electrode.  
   
   
       3 . The method of  claim 2 , wherein the gate insulating film of the transistor having the higher operation voltage is thicker than the gate insulating film of the transistor having the lower operation voltage.  
   
   
       4 . The method of  claim 1 , wherein each transistor includes an LDD region subject to said LDD implantation, the oxidation process causing thermal diffusion of the LDD regions in the transistor having a higher threshold voltage so that a junction depth of the LDD regions deepen.  
   
   
       5 . The method of  claim 2 , wherein each transistor includes an LDD region subject to said LDD implantation, the oxidation process causing thermal diffusion of LDD regions in the transistor having a higher operation voltage so as to ensure a smooth transition between the LDD region and adjacent n-impurity or p-impurity regions.  
   
   
       6 . The method of  claim 1 , wherein said transistors further comprise PMOS and NMOS transistors, at least one high-voltage and low-voltage PMOS transistor, and at least one high-voltage and low-voltage NMOS transistor.  
   
   
       7 . The method of  claim 6 , wherein threshold voltage values of the transistors are adjusted by using a mask to implant p impurities into an NMOS region of the NMOS transistors, and n impurities into a PMOS region of PMOS transistors so as to form a channel in each transistor.  
   
   
       8 . The method of  claim 7 , wherein the p impurities comprise at least one of boron or indium and the n impurities comprise at least one of phosphorous, arsenic, or antimony.  
   
   
       9 . The method of  claim 1 , wherein the gate electrode comprises poly-Si or amorphous-Si.  
   
   
       10 . The method of  claim 1 , wherein the oxidation process is carried out at a temperature of about 800-1000° C.