Split-gate type nonvolatile memory devices and methods for fabricating the same

Abstract

The nonvolatile memory device includes an electrically programmable transistor and a selection transistor. The selection transistor is connected between the electrically program transistor and a programmable voltage supply line. The selection transistor controls application of a voltage on the program voltage supply line to the electrically programmable transistor.

1 . A method of fabricating a nonvolatile memory device comprising: 
 forming a gate insulation layer on a semiconductor substrate;    forming a floating gate pattern on the gate insulation layer;    sequentially forming a tunnel insulation layer and a gate conductive layer on the semiconductor substrate, the tunnel insulation layer and the gate conductive layer covering the floating gate pattern;    patterning the gate conductive layer to form a control gate electrode on a sidewall and a portion of a top surface of the floating gate pattern and to form a selection gate electrode on the semiconductor substrate separated from the floating gate pattern; and    forming a common source region, a cell source region, and a drain region in the semiconductor substrate, the cell source region being formed in the semiconductor substrate between the selection gate electrode and the floating gate pattern, the drain region being formed in the semiconductor substrate on an opposite side of the control gate electrode from the selection gate electrode, and the common source region being formed in the semiconductor substrate on an opposite side of the selection gate from the floating gate pattern.    
   
   
       2 . The method of  claim 1 , wherein the forming a floating gate pattern step comprises: 
 sequentially forming a floating gate conductive layer and a hard mask layer on the gate insulation layer;    etching the hard mask layer to expose a portion of the floating gate conductive layer;    thermally oxidizing a top surface of the exposed floating gate conductive layer to form an oxide layer pattern having an elliptical cross-section;    removing the hard mask layer; and    etching the floating gate conductive layer using the oxide layer pattern as an etch mask.    
   
   
       3 . The method of  claim 2 , wherein the sequentially forming a tunnel insulation layer step forms the tunnel insulation layer on a top surface of the oxide layer pattern.  
   
   
       4 . The method of  claim 2 , further comprising: 
 performing a thermal process after the forming a floating gate pattern step to form a sidewall oxide layer on sidewalls of the floating gate pattern.    
   
   
       5 . The method of  claim 4 , further comprising: 
 forming a nitride layer spacer covering the sidewall oxide layer such that a height of the nitride layer spacer is less than a height of the sidewall oxide layer.    
   
   
       6 . The method of  claim 2 , wherein the tunnel oxide layer is formed by forming a high temperature oxide (HTO) layer and annealing the resultant HTO layer.  
   
   
       7 . A method of fabricating a nonvolatile memory device comprising: 
 forming a plurality of active regions in a predetermined region of a semiconductor substrate;    forming a plurality of floating gate patterns disposed in an array, each floating gate pattern formed on one of the active regions;    sequentially forming a tunnel oxide layer and a gate conductive layer over the semiconductor substrate;    patterning the gate conductive layer to form selection gate lines and control gate lines crossing the active regions, the control gate lines being disposed at least partially on a column of the floating gates;    forming common source regions and cell source regions in the active regions, the common source regions being formed in the active regions between a pair of adjacent selection gate lines, and each cell source region being formed in the active regions between one of the selection gate lines and one of the floating gate electrodes; and    forming drain regions in the active regions on opposite side of the control gate lines from an adjacent selection gate line.    
   
   
       8 . The method of  claim 7 , wherein the patterning step forms the control gate lines such that the floating gates protrude from a control gate line toward one of the selection gate lines and the floating gates cover a top surface of an active region under the control gate line.  
   
   
       9 . The method of  claim 7 , wherein the forming a plurality of floating gate patterns step comprises: 
 sequentially forming a gate insulation layer, a floating gate conductive layer, and a hard mask layer over the semiconductor substrate;    patterning the hard mask layer to form a mesh-shaped hard mask pattern, the hard mask pattern exposing predetermined regions of the floating gate conductive layer on the active regions;    performing a thermal process, to form oxide layer patterns having elliptical cross-sections on the exposed predetermined regions of the floating gate conductive layer;    removing the hard mask pattern; and    patterning the floating gate conductive layer using the oxide layer patterns as an etch mask to form the floating gate patterns.    
   
   
       10 . The method of  claim 9 , wherein the sequentially forming a tunnel oxide layer step forms the tunnel oxide layer on the oxide layer pattern.  
   
   
       11 . The method of  claim 7 , further comprising: 
 performing a thermal process after the forming a plurality of floating gates step to form sidewall oxide layers on sidewalls of the floating gate patterns.    
   
   
       12 . The method of  claim 11 , further comprising: 
 forming a nitride layer spacer on the sidewall oxide layers, a height of the nitride layer spacer being less than a height of the sidewall oxide layer.    
   
   
       13 . The method of  claim 7 , wherein the tunnel oxide layer is formed by forming a high temperature oxide (HTO) layer and annealing the resultant HTO layer.  
   
   
       14 . A method of fabricating a nonvolatile memory device, comprising: 
 forming a selection transistor between an electrically programmable transistor and a program voltage supply line.    
   
   
       15 . The method of  claim 14 , further comprising: 
 forming the electrically programmable transistor.    
   
   
       16 . The method of  claim 15 , wherein the forming a selection transistor and the forming the electrically programmable transistor steps are performed concurrently.  
   
   
       17 . A method of programming a nonvolatile memory device, comprising: 
 applying a programming voltage to a program voltage line associated with an electrically programmable transistor; and    applying a transfer voltage to a selection transistor connected between the program voltage supply line and the electrically programmable transistor such that the programming voltage is applied to the electrically programmable transistor.    
   
   
       18 . The method of  claim 17 , further comprising: 
 applying a first predetermined voltage to an output of the electrically programmable transistor is connected; and    applying a second predetermined voltage to a control gate of the electrically programmable transistor.    
   
   
       19 . A method of preventing programming of nonvolatile memory device, comprising: 
 applying an off voltage to a selection transistor connected between a program voltage supply line and an electrically programmable transistor to prevent a voltage on the program voltage supply line from being transferred to the electrically programmable transistor.