Slew rate controlled output buffer

Abstract

An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, wherein the charging current causes a substantially linear ramp voltage to form at the gate of the output transistor, whereby the ramp voltage controls a slew rate of the output terminal voltage.

1 - 24 . (canceled)  
   
   
       25 . An output buffer, comprising: 
 a first circuit portion and a second circuit portion each coupled between an input terminal and an output terminal of the output buffer; and    a bias voltage generator that generates a first bias voltage for the first circuit portion and a second bias voltage for the second circuit portion, wherein the first bias voltage and second bias voltage are between a power supply rail voltage and ground;    wherein each circuit portion includes, 
 a capacitive element;  
 an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and  
 a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, the current generator biased by a corresponding one of the first bias voltage and the second bias voltage.  
   
   
   
       26 . The output buffer of  claim 25 , further comprising: 
 a switch transistor, coupled to the current generator and the capacitive element, configured to cause the charging current to be directed to the capacitive element responsive to the logic transition.    
   
   
       27 . The output buffer of  claim 26 , wherein the current generator includes: 
 a constant current source; and    a current mirror coupled to the current source, the capacitive element, and the switch transistor.    
   
   
       28 . The output buffer of  claim 26 , wherein the switch transistor includes: 
 a gate at least indirectly coupled to the input terminal; and    a source-drain path coupled    (i) between an output node of the current generator and the power supply rail voltage of the output buffer, and    (ii) in parallel with the capacitive element.    
   
   
       29 . The output buffer of  claim 26 , wherein the first circuit portion further includes a logic inverter coupled between the input terminal and a gate of the switch transistor of first circuit portion.  
   
   
       30 . The output buffer of  claim 26 , wherein the second circuit portion includes a logic inverter and an inverter/level-shifter coupled between the input terminal and a gate switch transistor of the second circuit portion.  
   
   
       31 . The output buffer of  claim 25 , further comprising: 
 a resistor coupled between the drain of the output transistor and the output terminal.    
   
   
       32 . The output buffer of  claim 25 , wherein the first bias voltage is approximately equal to the second bias voltage.  
   
   
       33 . The output buffer of  claim 32 , wherein an output impedance of the output buffer is set substantially in accordance with 
 (i) a size of the output transistor, and    (ii) the corresponding first and second bias voltages.    
   
   
       34 . The output buffer of  claim 32 , wherein: 
 the first bias voltage and the second bias voltage is approximately equal to ½ of the power supply rail voltage.    
   
   
       35 . The output buffer of  claim 34 , wherein the power supply rail voltage is approximately 3.0 volts and the first bias voltage and second bias voltage are approximately 1.5 volts.  
   
   
       36 . The output buffer of  claim 25 , wherein 
 the current generator and output transistor of the first circuit portion are constructed using transistors having respective transistor types, and    the current generator and output transistor of the second circuit portion are constructed using transistors having respective transistor types that are complementary to the transistor types of corresponding transistors in the first circuit portion.    
   
   
       37 . The output buffer of  claim 25 , wherein the output transistor of the first circuit portion is configured to pull-down the output terminal voltage responsive to a low-to-high logic transition at the input terminal.  
   
   
       38 . The output buffer of  claim 37 , wherein the output transistor of the second circuit portion is configured to pull-up the output terminal voltage responsive to a high-to-low logic transition at the output terminal.  
   
   
       39 . The output buffer of  claim 25 , wherein the capacitive element includes a transistor configured as a capacitor.  
   
   
       40 . The output buffer or  claim 25 , wherein the output buffer is a PCI-X I/O output buffer.  
   
   
       41 . The output buffer of  claim 25 , wherein: 
 the charging current of the first circuit portion charges the respective capacitive element so as to increase the voltage formed thereon; and    the charging current of the second circuit portion charges the respective capacitive element so as to decrease the voltage formed thereon.    
   
   
       42 . An output buffer responsive to an input signal, comprising: 
 a bias voltage generator for generating a first bias voltage, the first bias voltage between a power supply rail voltage of the output buffer and a ground;    a first output transistor; and    a first drive circuit, coupled to a gate of the first output transistor and the bias voltage generator, configured to 
 (i) control a slew rate of the first output transistor responsive to a first logic transition of the input signal, and  
 (ii) cause the first bias voltage and a size of the output transistor to set an output impedance of the output buffer.  
   
   
   
       43 . The output buffer of  claim 42 , wherein the bias voltage generator is configured to generate a second bias voltage that is between the power supply rail voltage and the ground, and the output buffer further comprises: 
 a second output transistor;    a second drive circuit, coupled to a gate of the second output transistor and the bias voltage generator, configured to 
 (i) control a slew rate of the second output transistor responsive to a second logic transition the of the input signal, and  
 (ii) cause the second bias voltage and a size of the second output transistor to set the output impedance of the output buffer.  
   
   
   
       44 . The output buffer of  claim 43 , wherein the first and second bias voltages are the same voltage.