Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate

Abstract

The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.

1 . A semiconductor device comprising semiconductor chips that are stacked atop each other and that are having a plurality of terminals for sending and receiving information or power to and from the outside, 
 the terminals being arranged in at least one row, a first region in which a test probe contacts the terminals and a second region in which wiring that sends and receives information or power to and from the outside is connected to the terminals being provided,    the first region and the second region being disposed in a staggered manner in a condition in which the terminals are arranged in the row.    
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein: 
 the terminals are formed so as to have a first side that extends in a first direction in which they are arranged in the row and a second side that extends in a second direction that is perpendicular to the first direction, the second side being longer than the first side.    
     
     
         3 . A method for manufacturing the semiconductor device as claimed in  claim 1 , comprising: 
 a testing step for testing the semiconductor chip by contacting the test probe to the first region; and    a wiring step for connecting wiring to the second region for sending and receiving information or power to and from the outside after the testing step is completed.    
     
     
         4 . A semiconductor device comprising a first semiconductor chip and a second semiconductor chip, stacked atop a support substrate having an external connection terminal, the first semiconductor chip and the second semiconductor chip sealed in one package, 
 the first semiconductor chip being a memory chip and positioned at a lower layer,    and further, the second semiconductor chip being a logic chip and positioned at a layer above the first semiconductor chip.    
     
     
         5 . A semiconductor device comprising a memory chip and a logic chip stacked atop a support substrate having an external connection terminal, the memory chip and the logic chip sealed in one package, 
 a test terminal for a memory chip test being provided on the memory chip, the test terminal being directly connected to the external connection terminal.    
     
     
         6 . A semiconductor device comprising a first and a second semiconductor chips on which an alignment mark is formed for mutual alignment and which are stacked in one package, 
 the alignment mark being formed on a cover film formed on a chip surface.    
     
     
         7 . The semiconductor device as claimed in  claim 6 , wherein: 
 the alignment mark and a semiconductor chip pad are provided jointly.    
     
     
         8 . The semiconductor device as claimed in  claim 6 , wherein: 
 the alignment mark and a semiconductor chip pad are provided jointly, and    the pad is a non-bonding pad.    
     
     
         9 . The semiconductor device as claimed in  claim 6 , wherein: 
 an alignment mark provided on the first semiconductor chip and an alignment provided on the second semiconductor chip have an identical shape.    
     
     
         10 . A semiconductor device comprising a second semiconductor chip stacked atop a first semiconductor chip in one package, 
 a fuse window for redundancy being formed on the first semiconductor chip,    the fuse window being positioned at either a position between terminals formed on the first semiconductor chip and terminals formed on the second semiconductor chip, or at a position between an outer periphery of the first semiconductor chip and an outer periphery of the second semiconductor chip where no terminal exists, or at a position outside of a position at which terminals are formed on the first semiconductor chip.    
     
     
         11 . A semiconductor device comprising a plurality of semiconductor chips stacked to be mounted in one package, 
 a cover film being formed at least on such a region of the semiconductor chip positioned at a lower layer as that on which rests the semiconductor chip positioned at an upper layer thereof.    
     
     
         12 . A semiconductor device mounting a memory chip and a logic chip in one package, 
 test signal wiring for the memory chip wired directly between the memory chip and the logic chip, a test auxiliary circuit provided for the logic chip, the test signal being supplied via the auxiliary circuit to an external connection terminal provided on the package.    
     
     
         13 . A semiconductor device stacking so as to mount a plurality of semiconductor chips in one package, 
 a position of terminals that are both provided on a semiconductor chip which is positioned at a lower layer and that are connected to a semiconductor chip positioned at an upper layer being disposed near an outer periphery of the semiconductor chip positioned at the upper layer.    
     
     
         14 . A semiconductor device stacking so as to mount a plurality of semiconductor chips in one package, 
 a position of a terminal that is both provided on a semiconductor chip which is positioned at a lower layer and that is connected to a semiconductor chip positioned at an upper layer being disposed near an outer periphery of the semiconductor chip positioned at the upper layer, and    logic circuit groups being formed on both sides of a row of terminals formed on the semiconductor chip positioned at the lower layer.    
     
     
         15 . The semiconductor device as claimed in  claim 14 , wherein: 
 connecting wiring is provided at a position between the pair of adjacent terminals for connecting the logic circuit groups to each other.    
     
     
         16 . A semiconductor device sealing a first semiconductor chip having a first function and a second semiconductor chip having a second function in one package, 
 the first semiconductor chip being divided into a plurality of functional chips and disposed with open spaces, the second semiconductor chip being stacked above the divided plurality of functional chips.    
     
     
         17 . The semiconductor device as claimed in  claim 16 , wherein: 
 the first semiconductor device is a memory chip and the second semiconductor chip is a logic chip, and also,    the memory chip being divided according to storage capacities when the memory chip is divided.    
     
     
         18 . The semiconductor device as claimed in  claim 16 , wherein: 
 separation distances of the open spaces are set so as to permit entry of a sealing resin during resin sealing.    
     
     
         19 . The semiconductor device as claimed in  claim 16 , wherein: 
 a thickness of the first semiconductor chip is greater than a thickness of the second semiconductor chip.    
     
     
         20 . The semiconductor device as claimed in  claim 16 , wherein: 
 a third chip is provided so as to cover the openings at a side of the divided functional chips; and    a die bonding material fills a portion surrounded by the divided functional chips and the third chip.    
     
     
         21 . The semiconductor device as claimed in either  claim 5  or  claim 12 , wherein: 
 the test signal is normally a signal of a combination of a plurality of control signals to express a command for executing the memory operation mode.    
     
     
         22 . The semiconductor device as claimed in either  claim 5  or  claim 12 , wherein: 
 the test signal is one of either a control signal that deactivates the entire memory, a signal that deactivates a memory input or output terminals, a control signal used during burn-in or a control information signal used in the memory.    
     
     
         23 . The semiconductor device as claimed in  claim 14 , wherein: 
 signal wiring for the logic circuit groups is provided on both sides of the row of terminals formed on the semiconductor chip positioned at the lower layer.    
     
     
         24 . A semiconductor device comprising: 
 a plurality of semiconductor chips having a first function; and    a second semiconductor chip having a second function, the first and second semiconductor chips being sealed in one package.    
     
     
         25 . The semiconductor device as claimed in  claim 24 , wherein: 
 the plurality of semiconductor chips having the first function and the second semiconductor chips are stacked in the package.    
     
     
         26 . The semiconductor device as claimed in  claim 24 , wherein: 
 the first function and the second function are different functions.    
     
     
         27 . The semiconductor device as claimed in  claim 24 , wherein: 
 the semiconductor chip having the first function is a memory chip and the semiconductor chip is a logic chip; and    power wiring and signal wiring being provided between the logic chip and an external connection terminal,    only power wiring being provided between the memory chip and the external connection terminal,    only signal wiring being provided between the memory chip and the logic chip.