Non-volatile semiconductor memory and method of manufacturing the same

Abstract

A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon semiconductor substrate, and impurity diffusion layers are formed on the bottom surfaces of the grooves. A gate insulating film is then formed on the p-type silicon semiconductor substrate. This gate insulating film has a three-layer structure in which a first insulating film made of a silicon oxide film, a charge capturing film made of a silicon nitride film, and a second insulating film made of a silicon oxide film, are laminated in this order. A gate electrode is then formed on the gate insulating film. A convexity formed by the grooves serves as the channel region of the non-volatile semiconductor memory. Even if the device size is reduced, an effective channel length can be secured in this non-volatile semiconductor memory. Thus, excellent stability and reliability can be achieved.

1 - 6 . (canceled)  
   
   
       7 . A method of manufacturing a non-volatile semiconductor memory that has a charge capturing region in a gate insulating film formed between a semiconductor substrate and a gate electrode, 
 the method comprising the steps of:    forming grooves in the semiconductor substrate that serves as a first conductive member;    forming impurity diffusion layers that serve as a second conductive member on the bottom surfaces of the grooves; and    forming the gate insulating film on the semiconductor substrate having the impurity diffusion layers formed thereon, the gate insulating film including a charge capturing film in which the charge capturing region is to be formed.    
   
   
       8 . The method according to  claim 7 , wherein the step of forming grooves on the semiconductor substrate includes the step of forming a third insulating film on the semiconductor substrate prior to the formation of the grooves.  
   
   
       9 . The method according to  claim 7 , wherein the step of forming the gate insulating film on the semiconductor substrate includes the steps of: 
 forming a first insulting film on the semiconductor substrate having the impurity diffusion layers formed thereon;    forming the charge capturing film on the first insulating film;    removing the first insulating film and the charge capturing film from the upper surface of a convexity formed by the grooves in the semiconductor substrate; and    forming a fourth insulating film on the upper surface of the convexity.    
   
   
       10 . The method according to  claim 7 , further including the steps of: 
 removing the gate insulating film from the bottom surfaces of the grooves and the upper surface of the convexity formed by the grooves; and    forming a fourth insulating film on the parts of the semiconductor substrate from which the gate insulating film has been removed, the steps being carried out after the step of forming the gate insulating film on the semiconductor substrate.    
   
   
       11 . The method according to  claim 8 , further comprising the steps of: 
 removing the gate insulating film from the bottom surfaces of the grooves; and    forming a fourth insulating film on the parts of the semiconductor substrate from which the gate insulating film has been removed,    the steps being carried out after the step of forming the gate insulating film on the semiconductor substrate.    
   
   
       12 . A method of manufacturing a non-volatile semiconductor memory that has a charge capturing region in a gate insulating film formed between a semiconductor substrate and a gate electrode, 
 the method comprising the steps of:    forming an impurity diffusion layer that serves as a second conductive member on the semiconductor substrate that serves as a first conductive member; forming a groove in the semiconductor substrate having the impurity diffusion layer formed thereon; and    forming the gate insulating film on the semiconductor substrate having the groove formed therein, the gate insulating film including a charge capturing film in which the charge capturing region is to be formed.    
   
   
       13 . The method according to  claim 12 , wherein the step of forming the groove in the semiconductor substrate includes the step of forming a third insulating film on the semiconductor substrate having the impurity diffusion layer formed thereon, the step being carried out prior to the formation of the groove.  
   
   
       14 . The method according to  claim 12 , wherein the step of forming the gate insulating film on the semiconductor substrate includes the steps of: 
 forming a first insulating film on the semiconductor substrate having the groove formed therein;    forming the charge capturing film on the first insulating film;    removing the first insulating film and the charge capturing film from the upper surfaces of convexities formed by the groove; and    forming a fourth insulating film on the upper surfaces of the convexities.    
   
   
       15 . The method according to  claim 12 , further comprising the steps of: 
 removing the gate insulating film from the bottom surface of the groove and the upper surfaces of the convexities formed by the groove; and    forming a fourth insulating film on the parts of the semiconductor substrate from which the gate insulating film has been removed,    the steps being carried out after the step of forming the gate insulating film on the semiconductor substrate.    
   
   
       16 . The method according to  claim 13 , further comprising the steps of: 
 removing the gate insulating film from the bottom surface of the groove; and    forming a fourth insulating film on the parts of the semiconductor substrate from which the gate insulating film has been removed,    the steps being carried out after the step of forming the gate insulating film on the semiconductor substrate.    
   
   
       17 . The method according to  claim 12 , wherein the step of forming the groove includes the step of making the groove narrower toward the inside of the semiconductor substrate.