Programmable digital image processor

Abstract

A programmable image transform system has a programmable addressing and arithmetic blocks. In the programmable addressing block, an input address generator has an input addressing microsequencer and an input addressing memory that stores an input addressing procedure. The microsequencer executes the input addressing procedure to generate addresses from which to request image data. In the programmable arithmetic block, an arithmetic block memory stores an image processing procedure and a microsequencer executes the image processing procedure using the image data to generate transformed image data.

1 - 46 . (canceled)  
   
   
       47 . An image processor for processing image data in a system, said system having a microprocessor, said image processor comprising: 
 an arithmetic processing block including a buffer array and an N number of processing elements, said buffer array having an M number of rows and an N+1 number of columns, each of said N+1 number of columns defining each of an N+1 number of memory banks, wherein each of said N number of processing elements is associated with a corresponding one of said N+1 number of memory banks, and wherein (N+1)th memory bank of said N+1 number of memory banks provides boundary data for Nth processing element of said N number of processing elements;    a controller configured to control said N number of processing elements, said controller being in communication with said microprocessor of said system.    
   
   
       48 . The image processor of  claim 47 , wherein (N+1)th memory bank of said N+1 number of memory banks provides said boundary data for said Nth processing element of said N number of processing elements while convolutional algorithm is being applied to said image data.  
   
   
       49 . The image processor of  claim 47 , wherein said controller reads said image data in one of said N+1 number of memory banks, performs computation on said image data, and stores said images data in a different one of said N+1 number of memory banks.  
   
   
       50 . The image processor of  claim 47 , wherein said controller is a SIMD controller and simultaneously controls said N number of processing elements.  
   
   
       51 . The image processor of  claim 47  further comprising a programmable input addresser for transferring said image data from a data source to said arithmetic processing block by providing a source address onto a source address path, said source address identifying said data source.  
   
   
       52 . The image processor of  claim 47  further comprising a programmable output addresser for transferring said image data from said arithmetic processing block to a memory by providing a write address onto a write path, said write address identifying a write address in said memory for storage of said image data.  
   
   
       53 . The image processor of  claim 47  further comprising a Huffman encoder for encoding said image data received from said controller to generate an encoded image data, and a Huffman decoder for decoding said encoded image data.  
   
   
       54 . The image processor of  claim 53  further comprising one or more Huffman control registers for use by said Huffman encoder and said Huffman decoder.  
   
   
       55 . An image processor for processing image data in a system, said system having a microprocessor, said image processor comprising: 
 an arithmetic processing means for processing said image data, said arithmetic processing means including a buffer array and an N number of processing elements means for controlling said buffer array, said buffer array having an M number of rows and an N+1 number of columns, each of said N+1 number of columns defining each of an N+1 number of memory banks, wherein each of said N number of processing elements means is associated with a corresponding one of said N+1 number of memory banks, and wherein (N+1)th memory bank of said N+1 number of memory banks provides boundary data for Nth processing element means of said N number of processing elements means;    a controller means for controlling said N number of processing elements, said controller being in communication with said microprocessor of said system.    
   
   
       56 . The image processor of  claim 55 , wherein (N+1)th memory bank of said N+1 number of memory banks provides said boundary data for said Nth processing element means of said N number of processing elements means while convolutional algorithm is being applied to said image data.  
   
   
       57 . The image processor of  claim 55 , wherein said controller means reads said image data in one of said N+1 number of memory banks, performs computation on said image data, and stores said images data in a different one of said N+1 number of memory banks.  
   
   
       58 . The image processor of  claim 55 , wherein said controller means is a SIMD controller and simultaneously controls said N number of processing elements means.  
   
   
       59 . The image processor of  claim 55  further comprising a programmable input addresser means for transferring said image data from a data source to said arithmetic processing means by providing a source address onto a source address path, said source address identifying said data source.  
   
   
       60 . The image processor of  claim 55  further comprising a programmable output addresser means for transferring said image data from said arithmetic processing means to a memory by providing a write address onto a write path, said write address identifying a write address in said memory for storage of said image data.  
   
   
       61 . The image processor of  claim 55  further comprising a Huffman encoder means for encoding said image data received from said controller means to generate an encoded image data, and a Huffman decoder means for decoding said encoded image data.  
   
   
       62 . The image processor of  claim 61  further comprising one or more Huffman control registers for use by said Huffman encoder and said Huffman decoder.  
   
   
       63 . A method for use by an image transform processor for processing image data, the method comprising: 
 receiving the image data, using a programmable arithmetic processor, from a data source over a data path    processing the image data, using the programmable arithmetic processor, wherein the programmable arithmetic processor comprises a first set of local buffers and a second set of local buffers;    using each buffer in the first set of local buffers alternately for fetching input image data;    using each buffer in the second set of local buffers alternately for storing output image data; and    controlling transfer of the image data, using a programmable input addresser, from the data source to the programmable arithmetic processor by providing a source address onto a source address path, wherein the source address identifies the data source.    
   
   
       64 . The method of  claim 63  further comprising: 
 controlling transfer of the image data to the programmable arithmetic processor by providing a storage address to the programmable arithmetic processor, wherein the storage address identifies a location within the programmable arithmetic processor for storage of the image data.    
   
   
       65 . The method of  claim 63 , wherein the data source being a frame capture processor, and the source address identifying the frame capture processor.  
   
   
       66 . The method of  claim 63 , wherein the data source being a memory, the source address being a memory address identifying a location of the image data within the memory.  
   
   
       67 . The method of  claim 63 , wherein the data source being a memory, the source address path being a read address bus coupled between the programmable input addresser and the memory, the source address being a memory address identifying a location of the image data within the memory.  
   
   
       68 . The method of  claim 63  further comprising: 
 controlling transfer of the image data, using a programmable output addresser, from the programmable arithmetic processor to a memory by providing a write address onto a write path, the write address identifying a write address in the memory for storage of the image data.    
   
   
       69 . The method of  claim 68 , wherein the write path is a write address bus electrically connected to the programmable output addresser and the memory.  
   
   
       70 . The method of  claim 68 , wherein the programmable output addresser further controlling transfer of the image data by providing a retrieval address to the programmable arithmetic processor, the retrieval address identifying a location within the programmable arithmetic processor for retrieval of the image data.  
   
   
       71 . The method of  claim 70 , wherein the retrieval location within the programmable arithmetic processor is a buffer.  
   
   
       72 . The method of  claim 70 , wherein the retrieval location within the programmable arithmetic processor is at least one buffer of a plurality of buffers.  
   
   
       73 . The method of  claim 63  further comprising: 
 controlling transfer of the image data, using a programmable output addresser, from the programmable arithmetic processor to a memory by: 
 (i) providing a write address onto a write address bus coupled between the programmable output addresser and the memory, the write address identifying a write address in the memory for storage of the image data, and  
 (ii) providing a retrieval address to the programmable arithmetic processor, the retrieval address identifying a local buffer within the programmable arithmetic processor for retrieval of the image data.