US2005158910A1PendingUtilityA1

Protective layer for use in packaging a semiconductor die and method for forming same

45
Assignee: MICRON TECHNOLOGY INCPriority: Mar 18, 2003Filed: Mar 15, 2005Published: Jul 21, 2005
Est. expiryMar 18, 2023(expired)· nominal 20-yr term from priority
Inventors:Tongbi JiangZhiping YinMike Connell
H10W 74/016H10W 74/147H10W 74/43
45
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The present invention provides a semiconductor device having a protective layer for use in packaging the semiconductor device. The apparatus includes a dielectric layer, a first passivation layer formed above the dielectric layer, and a protective layer formed above the first passivation layer, the protective layer adapted to reduce stress defect failures in the semiconductor device when packaged.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device, comprising: 
 a dielectric layer;    a first passivation layer formed above the dielectric layer; and    a protective layer formed above the first passivation layer, the protective layer adapted to reduce stress defect failures in the semiconductor device when packaged.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the first passivation layer is a silicon nitride passivation layer.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the protective layer is a silicon carbide protective layer.  
   
   
       4 . The semiconductor device of  claim 1 , further comprising a plurality of metal structures disposed above a portion of the dielectric layer and below a portion of the first passivation layer.  
   
   
       5 . The semiconductor device of  claim 1 , further comprising: 
 a substrate deployed above the protective layer; and    a mold compound deposited between the substrate and the protective layer, wherein the mold compound includes at least one filler particle.    
   
   
       6 . The semiconductor device of  claim 5 , wherein the mold compound is an epoxy-based compound.  
   
   
       7 . The semiconductor device of  claim 1 , further comprising a second passivation layer formed above the protective layer.  
   
   
       8 . The semiconductor device of  claim 7 , wherein the second passivation layer comprises a polymer layer.  
   
   
       9 . The semiconductor device of  claim 8 , wherein the polymer layer is formed of at least one of a polyimide material, a Cardo material, an epoxy material, a benzocyclobutene material, a polybenzoxazole material, and a silicon material.  
   
   
       10 . The semiconductor device of  claim 1 , wherein the protective layer has a thickness of about 1000-3000 Å.  
   
   
       11 . The semiconductor device of claims  1 , wherein the dielectric layer comprises a plurality of transistors and interconnect structures formed above a silicon substrate.  
   
   
       12 . A method of forming a semiconductor device, comprising: 
 forming a dielectric layer;    forming a first passivation layer above the dielectric layer; and    forming a protective layer above the first passivation layer, the protective layer adapted to reduce stress defect failures in the semiconductor device when packaged.    
   
   
       13 . The method of  claim 12 , wherein forming the first passivation layer comprises forming a silicon nitride passivation layer.  
   
   
       14 . The method of  claim 13 , wherein forming the silicon nitride passivation layer comprises forming the silicon nitride passivation layer using at least one of a chemical vapor deposition (CVD) process, a low-pressure CVD (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a physical vapor deposition (PVD) process, and a sputtering process.  
   
   
       15 . The method of  claim 12 , wherein forming the protective layer comprises forming a silicon carbide protective layer.  
   
   
       14 . The method of  claim 13 , wherein forming the silicon carbide protective layer comprises forming the silicon carbide protective layer using at least one of a chemical vapor deposition (CVD) process, a low-pressure CVD (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and a physical vapor deposition (PVD) process, and a sputtering process.  
   
   
       15 . The method of  claim 12 , wherein forming the protective layer comprises forming the protective layer having a thickness of about 1000-3000 Å.  
   
   
       16 . The method of  claim 12 , wherein forming the first passivation layer comprises forming the first passivation layer by a spin-on process.  
   
   
       17 . The method of  claim 12 , wherein forming the protective layer comprises forming the protective layer by a spin-on process.  
   
   
       18 . The method of  claim 12 , further comprising: 
 deploying a substrate above the protective layer; and    depositing a mold compound between the substrate and the protective layer, wherein the mold compound includes at least one filler particle.    
   
   
       19 . The method of  claim 18 , wherein depositing the mold compound comprises depositing an epoxy-based compound.  
   
   
       20 . The method of  claim 12 , further comprising forming a second passivation layer above the protective layer.  
   
   
       21 . The method of  claim 20 , wherein forming the second passivation layer comprises forming the second passivation layer having a thickness ranging from about 5000 Å to about 500,000 Å.  
   
   
       22 . The method of  claim 20 , wherein forming the second passivation layer comprises forming a polymer layer.  
   
   
       23 . The method of  claim 22 , wherein forming the polymer layer comprises forming the polymer layer from at least one of a polyimide material, a Cardo material, an epoxy material, a benzocyclobutene material, a polybenzoxazole material, and a silicon material.

Join the waitlist — get patent alerts

Track US2005158910A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.