Memory device supporting a dynamically configurable core organization

Abstract

Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

1 . A dynamically configurable memory comprising: 
 a. configuration logic having a configuration-logic input terminal adapted to receive data indicative of a first or second memory core configuration and a configuration-logic output terminal providing configuration signals corresponding to the first and second memory core configurations; and    b. a dynamic memory core having: 
 i. a plurality of physical memory banks, each bank having associated therewith at least one device data line; and  
 ii. a core control circuit including a memory-core control terminal connected to the configuration-logic output terminal and memory-core data terminals connected to respective ones of the device data lines;  
   c. wherein the first memory core configuration divides the memory core into a first collection of logical memory banks, each logical memory bank including a first number of the physical memory banks, where the first number is at least one; and    d. wherein the second memory core configuration divides the memory core into a second collection of logical memory banks, each logical memory bank including a second number of the physical memory banks, where the second number is greater than the first number.    
   
   
       2 . The configurable memory of  claim 1 , further comprising a mode register connected to the configuration logic and adapted to store a value indicative of the first or second core configuration.  
   
   
       3 . The configurable memory of  claim 1 , further comprising a plurality of input/output buffers connected to the core control circuit and adapted to send and receive data signals to and from the physical memory banks.  
   
   
       4 . The configurable memory of  claim 3 , further comprising a switch matrix connected to the input/output buffers.  
   
   
       5 . The configurable memory of  claim 4 , wherein the switch matrix is a crossbar switch.  
   
   
       6 . The configurable memory of  claim 1 , each physical memory bank further comprising a collection of sense amplifiers and a bank-select terminal.  
   
   
       7 . The configurable memory of  claim 6 , wherein each bank-select terminal is adapted to enable data in the respective physical memory bank to transfer to the sense amplifiers in the respective physical bank.  
   
   
       8 . The configurable memory of  claim 7 , wherein the bank-select terminals enable a first number of the physical memory banks in the first mode and enable a second number of the physical memory banks in the second mode.  
   
   
       9 . A memory system comprising: 
 a. a memory bus having a plurality of system data lines;    b. a first memory module having: 
 i. a first plurality of module pins connected to respective ones of the system data lines;  
 ii. a first plurality of memory banks having a corresponding first collection of device data lines; and  
 iii. a first core control circuit adapted to programmably connect the first collection of device data lines to a first subset of the system data lines; and  
   c. a second memory module having: 
 i. a second plurality of module pins connected to respective ones of the device data lines;  
 ii. a second plurality of memory banks having a corresponding second collection of device data lines; and  
 iii. a second core control circuit adapted to programmably connect the second collection of device data lines to a second subset of the system data lines different from the first subset of system data lines.  
   
   
   
       10 . The memory system of  claim 9 , wherein none of the system data lines in the first subset is a data line in the second subset.  
   
   
       11 . The memory system of  claim 9 , wherein the first memory module further includes a first mode register connected to the first core control circuit, and the second memory module further includes a second mode register connected to the second core control circuit.  
   
   
       12 . The memory system of  claim 9 , the first memory module further including a first switch matrix connected between the first collection of device data lines and the first plurality of module pins, and the second memory module further including a second switch matrix connected between the second collection of device data lines and the second plurality of module pins.  
   
   
       13 . The memory system of  claim 9 , wherein each of the first and second memory modules can be dynamically configured to operate in at least two memory configurations.  
   
   
       14 . The memory system of  claim 13 , wherein the first memory configuration provides a first data width and the second memory configuration provides a second data width.  
   
   
       15 . The memory system of  claim 14 , wherein the first memory module includes configuration logic adapted to automatically change the memory configuration from the first memory configuration to the second memory configuration if the second memory module is removed from the memory system.  
   
   
       16 . The memory system of  claim 13 , wherein the selected one of the first and second data widths depends on the number of memory modules in the memory system.  
   
   
       17 . The memory system of  claim 9 , wherein the first and second modules are physically identical memory modules.  
   
   
       18 . A memory system comprising: 
 a. a memory bus having a plurality of system data lines; and    b. at least one memory module having: 
 i. a plurality of module pins connected to respective ones of the system data lines;  
 ii. a plurality of memory banks;  
 iii. configuration and control logic connected to the memory banks and adapted to configure the memory banks to form one of several memory-width configurations; and  
 iv. a switch matrix connected between the memory banks and the plurality of module pins, the switch matrix adapted to programmably connect the memory banks to all or a subset of the system data pins.  
   
   
   
       19 . The memory system of  claim 18 , wherein the memory-width configuration depends upon the number of memory modules in the system.