Static random access memory

Abstract

A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.

1 . A memory cell comprising: 
 a pass transistor, a pull-down transistor, a first power supply, a second power supply, a precharge circuit, and a decoder circuit, each transistor having a threshold voltage, a gate and a channel, the channel having a first end and a second end, the second end of the channel of the pass transistor coupled to the first end of the channel of the pull-down transistor, and the second end of the channel of the pull-down transistor coupled to a ground connection, the first end of the channel of the pass transistor coupled to the first power supply via the precharge circuit and the gate of the pass transistor coupled to the second power supply via the decoder circuit, the first power supply and the second power supply each having a different power supply voltage.    
   
   
       2 - 31 . (canceled)