Memory devices

Abstract

A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to within the trench. First isolation material is removed effective to form a line trench into a desired local interconnect. Conductive material is formed therewithin. A second isolation material is deposited over the first isolation material, over the conductive material within the isolation trench and within the line trench. At least some first and second isolation material is removed in at least one common removing step. Integrated circuitry includes a substrate comprising trench isolation material. A local interconnect line is received within a trench formed within the isolation material. The local interconnect includes at least two different conductive materials. One of the conductive materials lines the trench. Another of the conductive materials is received within a conductive trench formed by the one. Other implementations are disclosed.

1 - 48 . (canceled)  
   
   
       49 . A memory device comprising: 
 first and second transistors formed within a semiconductor substrate, the semiconductor substrate comprising trench isolation material between the first and second transistors, the trench isolation material comprising first and second opposing sidewalls in at least one cross section;    a trench formed within the trench isolation material; and    a local interconnect line received within the trench and electrically connecting the a source/drain region of the first transistor with a gate of the second transistor.    
   
   
       50 . The device of  claim 49  wherein the first transistor, the second transistor, and the local interconnect line are components of an SRAM device.  
   
   
       51 . The device of  claim 50  wherein the local interconnect line electrically connects two gates of the SRAM device with source drain regions of two transistors.  
   
   
       52 . The device of  claim 49  further comprising insulative material received within the trench and over the local interconnect line.  
   
   
       53 . The device of  claim 49  wherein the local interconnect line comprises at least two different conductive materials, a first conductive material lining the trench and a second conductive material being received on the first conductive material.  
   
   
       54 . The device of  claim 53  further comprising insulative material received over the local interconnect line, a conductive trench being formed in the first conductive material, wherein the second conductive material is received within the conductive trench.  
   
   
       55 . The device of  claim 49  wherein the substrate further comprises: 
 a first conductivity type background region; and    a second conductivity type background region adjacent the first conductivity type background region, wherein the first sidewall extends along the first conductivity type background region, and the second sidewall extends along the second conductivity type background region.    
   
   
       56 . The device of  claim 55  wherein the first transistor is formed within the first conductivity type background region and the second transistor is formed within the second conductivity type background region.  
   
   
       57 . The device of  claim 55  wherein the local interconnect line is laterally centered between the first and second opposing sidewalls in the at least one cross section.  
   
   
       58 . The device of  claim 55  further comprising a boundary extending between the first and second conductivity type background regions, wherein the local interconnect line is received along the boundary.  
   
   
       59 . A memory device comprising: 
 a substrate comprising: 
 a first conductivity type background region;  
 an adjacent second conductivity type background region; and  
 a boundary extending therebetween;  
   a first transistor formed within the first conductivity type background region;    a second transistor formed within the second conductivity type background region;    trench isolation material received along the boundary and between the first and second transistors;    a trench formed within the trench isolation material and received along the boundary; and    a local interconnect line received within the trench, the line electrically connecting the first transistor with the second transistor.    
   
   
       60 . The device of  claim 59  wherein the trench isolation material comprises opposing outer sidewalls in at least one cross section, one of the sidewalls extending along at least the first region, the local interconnect line being laterally centered between the opposing outer sidewalls in the at least one cross section.  
   
   
       61 . The device of  claim 59  wherein the first transistor, the second transistor, and the local interconnect line are components of an SRAM device.  
   
   
       62 . The device of  claim 59  further comprising insulative material received within the trench and over the local interconnect line.  
   
   
       63 . The device of  claim 59  wherein the local interconnect line is received along the boundary.  
   
   
       64 . The device of  claim 59  wherein the local interconnect line comprises at least two different conductive materials, a first conductive material of the two different conductive materials lining the trench and a second conductive material of the two different conductive materials being received on the first conductive material.  
   
   
       65 . The device of  claim 64  further comprising insulative material received over the local interconnect line.  
   
   
       66 . A memory device comprising: 
 at least first and second pairs of transistors formed within a substrate, the first pair being electrically connected to one another by a first conductive line and the second pair being electrically connected to one another by a second conductive line, the substrate comprising trench isolation material between the first and second conductive lines;    a trench formed within the trench isolation material; and    a local interconnect line received within the trench and electrically connecting the first conductive line with the second conductive line.    
   
   
       67 . The memory device of  claim 66  wherein the local interconnect line comprises at least first and second conductive portions, the first conductive portion lining the trench and comprising a conductive trench, and the second conductive portion being received within the trench.  
   
   
       68 . The memory device of  claim 66  wherein the substrate further comprises at least first and second conductivity type background regions, one of the first pair of transistors being formed within the first conductivity type background region and the other of the first pair of transistors being formed with the second type background region.  
   
   
       69 . The memory device of  claim 68  wherein the first conductivity type background region comprises n-type conductivity material and the second type background region comprises p-type conductivity material.  
   
   
       70 . The memory device of  claim 68  wherein the substrate further comprises a boundary between the first and second regions, the local interconnect line being received over the boundary.