Thin film transistors and methods of forming thin film transistors

Abstract

A method of forming a thin film transistor over a substrate is provided whereby at least one of the source region or the drain region is conductively doped while preventing conductivity doping of the channel region without any masking of the channel region occurring by any separate masking layer. A method includes, a) providing a substrate having a node to which electrical connection is to be made; b) providing a first electrically insulative dielectric layer over the substrate; c) providing an electrically conductive gate layer over the first dielectric layer; d) providing a second electrically insulative dielectric layer over the electrically conductive gate layer; e) providing a contact opening through the second dielectric layer, the electrically conductive gate layer and the first dielectric layer; the contact opening defining projecting sidewalls; f) providing a gate dielectric layer within the contact opening laterally inward of the projecting sidewalls; g) providing a layer of semiconductive material over the second dielectric layer and within the contact opening against the gate dielectric layer and in electrical communication with the node; the semiconductive material within the contact opening defining an elongated and outwardly extending channel region the electrical conductance of which can be modulated by means of the adjacent electrically conductive gate and gate dielectric layers; and h) conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region of a thin film transistor. Thin film transistor constructions are also disclosed.

1 - 35 . (canceled)  
   
   
       36 . A wafer comprising:  
     a transistor comprising: 
 a substrate;  
 a gate provided over the substrate and substantially surrounding an opening;  
 a first source/drain region;  
 a second source/drain region;  
 semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions, wherein at least a portion of the channel is formed within the opening; and  
 dielectric material formed intermediate the gate and the semiconductive material.  
 
   
   
       37 . The wafer of  claim 36 , wherein the semiconductive material partially fills the opening within the gate.  
   
   
       38 . The wafer of  claim 36  further comprising an electrically insulative layer over the substrate and below the gate.  
   
   
       39 . The wafer of  claim 36 , wherein the transistor comprises a thin film transistor.  
   
   
       40 . The wafer of  claim 36 , wherein the dielectric material is formed within the opening, and wherein the dielectric material and the semiconductive material completely fill the opening within the gate.  
   
   
       41 . The wafer of  claim 36 , wherein at least a portion of the first source/drain region is formed above the opening of the gate.  
   
   
       42 . The wafer of  claim 41 , wherein at least a portion of the second source/drain region is formed below the opening of the gate.  
   
   
       43 . The wafer of  claim 36 , wherein the gate laterally surrounds dielectric material.  
   
   
       44 . The wafer of  claim 36 , wherein the dielectric material laterally surrounds the channel formed within the opening.  
   
   
       45 . The wafer of  claim 36 , wherein at least a portion of the first source/drain region is formed within the semiconductive material.  
   
   
       46 . The wafer of  claim 36 , wherein at least a portion of the first source/drain region is formed within the substrate.  
   
   
       47 . The wafer of  claim 36 , wherein the channel is formed elevationally above at least one of the first and second source/drain regions.  
   
   
       48 . The wafer of  claim 36 , wherein the channel comprises an elongated structure extending substantially perpendicularly to an upper surface of the substrate.  
   
   
       49 . A wafer comprising:  
     a transistor comprising: 
 a substrate;  
 a gate provided over the substrate and substantially surrounding an opening, wherein the opening has a lateral cross-sectional dimension which is less than a minimum photolithographic feature size utilized for fabricating the transistor;  
 a first source/drain region;  
 a second source/drain region; and  
 semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions.  
 
   
   
       50 . The wafer of  claim 49 , wherein the channel is formed within the opening.  
   
   
       51 . The wafer of  claim 49 , wherein at least a portion of the first source/drain region is formed above the opening of the gate.  
   
   
       52 . The wafer of  claim 49 , wherein the gate laterally surrounds the channel.  
   
   
       53 . The wafer of  claim 49 , wherein the transistor comprises a gate dielectric between the gate and the channel, and wherein the gate dielectric laterally surrounds the channel.  
   
   
       54 . The wafer of  claim 49 , wherein at least a portion of the first source/drain region is formed above the opening, and wherein at least a portion of the second source/drain region is formed below the opening.  
   
   
       55 . The wafer of  claim 49 , wherein the transistor comprises a thin film transistor.  
   
   
       56 . The wafer of  claim 49  further comprising an electrically insulative layer over the substrate and below the gate.  
   
   
       57 . A semiconductor device comprising:  
     a transistor comprising: 
 a substrate;  
 a gate provided over the substrate and substantially surrounding an opening;  
 a first source/drain region comprising at least a portion formed partially below the opening;  
 a second source/drain region comprising at least a portion formed partially above the opening;  
 semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions; and  
 a gate dielectric formed intermediate the gate and the semiconductive material.  
 
   
   
       58 . The semiconductor device of  claim 57 , wherein the channel is formed within the opening.  
   
   
       59 . The semiconductor device of  claim 57 , wherein the transistor comprises a thin film transistor.  
   
   
       60 . A semiconductor device comprising:  
     a transistor comprising: 
 a substrate;  
 a gate provided over the substrate and substantially surrounding an opening, wherein the opening has a lateral cross-sectional dimension which is less than a minimum photolithographic feature size utilized for fabricating the transistor;  
 first and second source/drain regions;  
 semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions; and  
 a gate dielectric formed intermediate the gate and the channel.  
 
   
   
       61 . The semiconductor device of  claim 60 , wherein the channel is formed within the opening.  
   
   
       62 . The semiconductor device of  claim 60 , wherein the transistor comprises a thin film transistor.  
   
   
       63 . A transistor comprising: 
 a substrate;    a gate provided over the substrate and substantially surrounding an opening;    a first source/drain region comprising at least a portion formed partially below the opening;    a second source/drain region comprising at least a portion formed partially above the opening;    semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions; and    a gate dielectric intermediate the gate and the channel.    
   
   
       64 . The transistor of  claim 63 , wherein the channel is formed in the opening and partially fills the opening.  
   
   
       65 . The transistor of  claim 63  further comprising a thin film transistor.  
   
   
       66 . The transistor of  claim 63 , wherein the gate dielectric and the semiconductive material completely fill the opening within the gate.  
   
   
       67 . The transistor of  claim 63 , wherein the semiconductive material is provided within the opening and over the gate.  
   
   
       68 . The transistor of  claim 63 , wherein the opening is formed through an entirety of the gate.  
   
   
       69 . The transistor of  claim 63 , wherein at least a portion of the first source/drain region is formed within the semiconductive material.  
   
   
       70 . The transistor of  claim 63 , wherein at least a portion of the first source/drain region is formed within the substrate.  
   
   
       71 . A transistor comprising: 
 a substrate;    a gate provided over the substrate and substantially surrounding an opening over the substrate, the opening has a lateral cross-sectional dimension which is less than a minimum photolithographic feature size utilized for fabricating the transistor;    first and second source/drain regions; and    semiconductive material intermediate the first and second source/drain regions and comprising a channel.    
   
   
       72 . The transistor of  claim 71 , wherein at least a portion of at least one of the first and second source/drain regions is formed within the opening.  
   
   
       73 . The transistor of  claim 71 , wherein at least a portion of the semiconductive material is formed within the opening.  
   
   
       74 . The transistor of  claim 71  further comprising insulative material provided intermediate the gate and the semiconductive material.  
   
   
       75 . The transistor of  claim 71 , wherein at least a portion of at least one of the first and second source/drain regions is formed above the opening of the gate.  
   
   
       76 . The transistor of  claim 75 , wherein at least a portion of at least one of the first and second source/drain regions is formed below the opening of the gate.  
   
   
       77 . The transistor of  claim 71  further comprising a thin film transistor.