Semiconductor device

Abstract

The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.

1 . A semiconductor device comprising: 
 a resin sealing body;    a first power supply terminal that is exposed out of said resin sealing body to supply a first power supply potential;    a second power supply terminal that is exposed out of said resin sealing body to supply a second power supply potential, which is lower than said first power supply potential;    a control terminal that is exposed out of said resin sealing body to supply a control signal;    an output terminal that is exposed out of said resin sealing body;    a first field effect transistor whose source-drain path is series-connected between said first power supply terminal and said output terminal;    a second field effect transistor whose source-drain path is series-connected between said output terminal and said second power supply terminal;    a first control circuit that is connected to said control terminal to control a gate electrode of said first field effect transistor with said control signal; and    a second control circuit that is connected to said control terminal to control a gate electrode of said second field effect transistor with said control signal, wherein said first field effect transistor and said first control circuit are formed by a first semiconductor chip;    wherein said second field effect transistor is formed by a second semiconductor chip, which differs from said first semiconductor chip; and    wherein said first semiconductor chip and said second semiconductor chip are sealed in said resin sealing body.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein said first semiconductor chip is provided with said second control circuit, which controls the gate electrode of said second field effect transistor.  
     
     
         3 . The semiconductor device according to  claim 1 , wherein said first field effect transistor comprises a semiconductor substrate that includes a first main surface and a second main surface opposing to said first main surface; a gate insulation film that is formed on said first main surface of said semiconductor substrate; a gate electrode that is formed on said gate insulation film; source and drain semiconductor regions that are formed on said first main surface and both sides said gate electrode; and a channel formation semiconductor region that is formed on said first main surface, formed beneath said gate electrode and between said source and drain semiconductor regions.  
     
     
         4 . The semiconductor device according to  claim 1 , wherein the ON resistance of said second field effect transistor is smaller than the ON resistance of said first field effect transistor.  
     
     
         5 . The semiconductor device according to  claim 4 , wherein the ON time of said second field effect transistor is longer than the ON time of said first field effect transistor.  
     
     
         6 . The semiconductor device according to  claim 1 , wherein a diode is formed on said second semiconductor chip; an anode of said diode is electrically connected to a source of said second field effect transistor; and a cathode of said diode is electrically connected to a drain of said second field effect transistor.  
     
     
         7 . The semiconductor device according to  claim 1 , wherein said first semiconductor chip is mounted on a first chip mounting member; wherein said second semiconductor chip is mounted on a second chip mounting member; and wherein said first chip mounting member and said second chip mounting member are partially exposed out of said resin sealing body.  
     
     
         8 . The semiconductor device according to  claim 1 , wherein the main surfaces of said first semiconductor chip and said second semiconductor chip are provided with a metallic body, which is partially exposed out of said resin sealing body.  
     
     
         9 . The semiconductor device according to  claim 8 , wherein said metallic body is electrically connected not only to electrodes of said first semiconductor chip and said second semiconductor chip but also to leads.  
     
     
         10 . The semiconductor device according to  claim 1 , wherein a series circuit between said first field effect transistor and said second field effect transistor is a part of a DC-DC converter.  
     
     
         11 . A semiconductor device comprising: 
 a first semiconductor chip in which a high-side switch power transistor is formed; and    a second semiconductor chip in which a low-side switch power transistor is formed, the low-side switch power transistor being series-connected to said high-side switch power transistor, wherein    said first semiconductor chip and said second semiconductor chip are contained in the same resin sealing body;    wherein said first semiconductor chip is provided with a drive circuit for driving said high-side switch power transistor; and    wherein said high-side switch power transistor is formed by a horizontal power MOSFET, and said low-side switch power transistor is formed by a vertical power MOSFET.    
     
     
         12 . The semiconductor device according to  claim 11 , wherein said first semiconductor chip is mounted on a first chip mounting member; wherein said second semiconductor chip is mounted on a second chip mounting member; and wherein said first chip mounting member and said second chip mounting member are partially exposed out of said resin sealing body.  
     
     
         13 . The semiconductor device according to  claim 11 , wherein main surfaces of said first semiconductor chip and said second semiconductor chip are provided with a metallic body, which is partially exposed out of said resin sealing body.  
     
     
         14 . The semiconductor device according to  claim 13 , wherein said metallic body is electrically connected not only to electrodes of said first semiconductor chip and said second semiconductor chip but also to leads.  
     
     
         15 . The semiconductor device according to  claim 6 , wherein wiring between a source of said first field effect transistor and the drain of said second field effect transistor is electrically connected to output wiring of said power supply circuit; wherein, 
 (a) when said first field effect transistor turns ON, a first current flows from said first power supply potential, which is electrically connected to the drain of said first field effect transistor, to said output wiring via said first field effect transistor;    (b) wherein, when said first field effect transistor turns OFF, a second current flows from said second power supply potential, which is electrically connected to the source of said second field effect transistor, to said output wiring via said diode; and    wherein, (c) when said second field effect transistor turns ON, a third current flows from said second power supply potential to said output wiring via said second field effect transistor.    
     
     
         16 . The semiconductor device according to  claim 1 , wherein said second field effect transistor comprises a semiconductor substrate that includes a first main surface and a second main surface opposing to said first main surface; a groove that is formed from the first main surface to the second main surface of said semiconductor substrate; a gate insulation film that is formed on an inner wall surface of said groove; a gate electrode that is formed on said gate insulation film; a source semiconductor region that is formed on said first main surface and both sides said gate electrode; a channel formation semiconductor region that is formed on a side surface of said gate electrode and formed between said source and drain semiconductor regions; and a drain semiconductor region that is formed on said second main surface.