Method and apparatus for regulating the voltage supplied to a computer system

Abstract

A computer system having multiple components capable of being in either a wake or sleep state includes a controller and a voltage regulator. The controller may generate a power state status signal indicating the power states of the components, and this signal may be provided to the voltage regulator. In response, the voltage regulator increases its output voltage level to the components when the power state status signal indicates that the components enter a sleep state.

1 . A computer system comprising: 
 a controller to generate a power state status signal to indicate a power state of a first plurality of components of the computer system; and    a voltage regulator to supply a voltage level to the first plurality of components and to increase the voltage level to the first plurality of components when the first plurality of components enters a sleep state, as indicated by the power state status signal.    
   
   
       2 . The computer system of  claim 1 , wherein the voltage regulator is to decrease the voltage level to the first plurality of components when the first plurality of components enter a wake state, as indicated by the power state status signal.  
   
   
       3 . The computer system of  claim 1 , wherein the power state status signal is to further indicate a power state of at least a second component, the voltage regulator to supply the voltage level to the second component and to increase the voltage level to both the second component and to the first plurality of components when the first plurality of components enters a sleep state and a power state of the second component remains unchanged.  
   
   
       4 . The computer system of  claim 3  wherein the power state of the second component that remains unchanged is a sleep state.  
   
   
       5 . The computer system of  claim 3 , wherein the power state of the second component that remains unchanged is a wake state.  
   
   
       6 . The computer system of  claim 3 , wherein the voltage regulator is to decrease the voltage level to both the second component and to the first plurality of components when the first plurality of components enters a wake state and a power state of the second component remains unchanged.  
   
   
       7 . The computer system of  claim 1 , wherein the power state status signal is an SLP_S 3 # signal.  
   
   
       8 . The computer system of  claim 1 , wherein the fist plurality of components includes a hard disk drive.