US2005151263A1PendingUtilityA1

Wiring structure forming method and semiconductor device

Assignee: FUJITSU LTDPriority: Jan 8, 2004Filed: May 24, 2004Published: Jul 14, 2005
Est. expiryJan 8, 2024(expired)· nominal 20-yr term from priority
H10P 14/44H10W 20/062H10W 20/054H10W 20/043H10W 20/033H10P 14/40H10D 64/011
43
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

After a via hole to connect a lower wiring and an upper wiring not shown is formed in an insulating film using an etching stopper film and a hard mask, a base film made from tantalum is formed on the insulating film so as to cover an inner wall of the via hole by a one-step low-power bias sputtering method of the present invention. Thus, the base film with a thin and uniform film thickness covering a region from an inner wall surface of the via hole to the insulating film is obtained.

Claims

exact text as granted — not AI-modified
1 . A wiring structure forming method, comprising the steps of: 
 forming an opening in an insulating film over a substrate;    forming a base film over the insulating film in such a manner that the base film covers an inner wall surface of the opening by a sputtering method;    removing the base film over the insulating film other than that in the opening in such a manner that the base film remains only over the inner wall surface of the opening; and    embedding a conductive material in the opening with the base film therebetween, wherein the base film is formed in such a manner that a film thickness thereof in a portion other than the opening over the insulating film is equal to or less than {fraction (1/20)} of a diameter of the opening.    
     
     
         2 . The wiring structure forming method according to  claim 1 , wherein the base film is formed in such a manner that a film thickness thereof in a portion other than the opening over the insulating film is equal to or less than {fraction (1/30)} of a diameter of the opening.  
     
     
         3 . The wiring structure forming method according to  claim 1 , wherein the base film is formed in such a manner that a film thickness thereof over a bottom surface of the inner wall surface of the opening is not less than 20% nor more than 100% of a film thickness in a portion other than the opening over the insulating film.  
     
     
         4 . A wiring structure forming method, comprising the steps of: 
 forming an opening in an insulating film over a substrate;    forming a base film in such a manner that the base film covers only an inner wall surface of the opening and is not deposited over the insulating film other than that in the opening by a sputtering method; and    embedding a conductive material in the opening with the base film therebetween.    
     
     
         5 . The wiring structure forming method according to  claim 1 , wherein the base film is formed by the sputtering method under a condition of  
         1< Vd/Ve< 2  
       where Vd/Ve is a ratio of a deposition rate (Vd) of a material for the base film to an etching rate (Ve) thereof.  
     
     
         6 . The wiring structure forming method according to  claim 1 , wherein the base film is formed by plural sputtering steps comprising: 
 a first step under a condition of Vd/Ve>1; and    a second step under a condition of Vd/Ve<1 where Vd/Ve is a ratio of a deposition rate (Vd) of a material for the base film to an etching rate (Ve) thereof.    
     
     
         7 . The wiring structure forming method according to  claim 5 , wherein the base film is formed so as to cover only the inner wall surface of the opening and not to be deposited over the insulating film other than that in the opening.  
     
     
         8 . The wiring structure forming method according to  claim 1 , wherein when the base film is formed, a bias voltage is applied to the substrate.  
     
     
         9 . The wiring structure forming method according to  claim 8 , wherein the base film is formed under a condition that a target power is not less than 0.1 kW nor more than 5.0 kW and a bias voltage is not less than 100 W nor more than 450 W.  
     
     
         10 . The wiring structure forming method according to  claim 1 , wherein the base film is formed under a condition that a pressure of an atmosphere of a sputtering ion species is not less than 1×10 −2  Pa nor more than 1×10 −1  Pa.  
     
     
         11 . The wiring structure forming method according to  claim 1 , wherein the conductive material is copper or a conductive substance containing copper, and the opening includes at least a connection hole.  
     
     
         12 . The wiring structure forming method according to  claim 1 , wherein a material for the base film is at least one type selected from the group consisting of tantalum, titanium, tungsten, zirconium, and vanadium or a nitride containing the at least one type.  
     
     
         13 . A semiconductor device, comprising: 
 a semiconductor substrate;    an insulating film which is provided over said semiconductor substrate and in which an opening is formed;    a base film which covers only an inner wall surface of the opening; and    a conductive material which is embedded in the opening with said base film therebetween, wherein    said base film is a sputtering film covering the inner wall surface at a uniform film thickness and made from a uniform material.    
     
     
         14 . The semiconductor device according to  claim 13 , wherein said conductive material is copper or a conductive substance containing copper, and the opening includes at least a connection hole.  
     
     
         15 . The semiconductor device according to  claim 13 , wherein a material for said base film is at least one type selected from the group consisting of tantalum, titanium, tungsten, zirconium, and vanadium or a nitride containing the at least one type.

Join the waitlist — get patent alerts

Track US2005151263A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.