Metal oxide semiconductor field-effect transistor and associated methods

Abstract

A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

1 - 50 . (canceled)  
   
   
       51 . An integrated structure in a semiconductor wafer comprising: 
 at least one MOS field-effect transistor including an active region defining an active area on a surface of the substrate;    a silicide surface layer which at least partially covers the first active area,    at least one LDMOS transistor including a first active region which defines a first active area on the surface of the substrate; and    a first silicide surface layer which only partially covers the first active area.    
   
   
       52 . The integrated structure according to  claim 51 , wherein the LDMOS transistor comprises a gate structure, and the first active region of the LDMOS transistor comprises a drain region and a drift region; the first silicide surface layer covering the drain region and being interrupted in such a way that a portion of the drift region adjacent to the gate structure is not covered with silicide.  
   
   
       53 . The integrated structure according to  claim 52 , wherein at least one electrically insulating element is positioned on a surface of the non-silicide-covered portion of the drift region.  
   
   
       54 . The integrated structure according to  claim 52 , wherein the gate structure comprises a layer of conductive gate layer superimposed on a gate oxide layer positioned on the surface of the substrate; and wherein the LDMOS transistor comprises a second active region including a body region and a source region, each of the conductive gate layer and the second active region being covered with a corresponding layer of silicide.  
   
   
       55 . The integrated structure according to  claim 54 , wherein the gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness different from the first thickness.  
   
   
       56 . The integrated structure according to  claim 55 , wherein the first thickness of the first portion of the gate oxide layer is greater than the second thickness, the first portion being adjacent to the drift region and the second portion being adjacent to the body region.  
   
   
       57 . The integrated structure according to  claim 51 , wherein the semiconductor substrate comprises a lower portion having a first type of conductivity and an epitaxial layer thereon having the first type of conductivity, the epitaxial layer having a conductivity which is less than the conductivity of the lower portion, and the first and the second active regions being formed within the epitaxial layer.  
   
   
       58 . A method of manufacturing at least one MOS field-effect transistor and at least one LDMOS field-effect transistor integrated in a semiconductor substrate, the method comprising: 
 forming, in the substrate, two active regions of the at least one MOS transistor, the active regions defining corresponding active areas on a surface of the substrate;    forming, in the substrate, a first and a second active region of the at least one LDMOS transistor, the first and second active regions defining a first and a second active area on the surface of the substrate,    forming a layer of silicide on at least one portion of each of the two active areas of the at least one MOS transistor; and    forming a first and a second layer of silicide on the first and second active areas of the at least one LDMOS transistor, the first layer of silicide only partially covering the first active area.    
   
   
       59 . The method according to  claim 58 , further comprising: 
 forming, on the substrate, a gate structure of the at least one LDMOS transistor, the gate structure including a gate oxide layer and a conductive gate layer; and    forming a further layer of silicide on a surface of the gate oxide layer.    
   
   
       60 . The method according to  claim 59 , wherein the first active region comprises a drain region and a drift region, and the second active region comprises a body region and a source region; and wherein forming the first and second layers of silicide comprises forming the first layer of silicide to cover the drain region and so that a portion of the drift region adjacent to the gate structure is not silicidized.  
   
   
       61 . The method according to  claim 60 , wherein forming the first and second layers of silicide further comprises: 
 shielding the portion of the drift region via a protective element located at least on the portion;    depositing a layer of refractory metal on the first active area, on the second active area and on the shielding element; and    heat treating the wafer so that the layer of refractory metal reacts with portions of the first and second active area on which it is deposited to form silicide.    
   
   
       62 . The method according to  claim 61 , wherein shielding the portion of the drift region comprises forming a layer of protective material on the substrate and delimiting the protective element via masking and etching the layer of protective material.  
   
   
       63 . The method according to  claim 60 , wherein the gate structure of the at least one LDMOS transistor comprises an insulating gate layer positioned on the substrate and including a first portion having a first thickness and a second portion having a second thickness which is less than the first thickness, the first portion being adjacent to the drift region.  
   
   
       64 . The method according to  claim 60 , wherein forming the gate structure comprises: 
 forming at least one oxide layer on the surface of the substrate, a portion of the oxide layer forming the insulating gate layer;    forming a layer of polysilicon on a surface of the oxide layer, a portion of the layer of polysilicon forming the conductive gate layer;    masking and etching the layer of polysilicon to form at least a first lateral wall of the conductive gate layer and a first aperture in the polysilicon layer; and    further masking and etching the polysilicon layer to form at least a second lateral wall of the conductive gate layer and a second aperture in the polysilicon layer.    
   
   
       65 . The method according to  claim 64 , further comprising inclined ion implantation through the first aperture and through the second aperture to form the body region and the drift region, the inclined ion implantation providing for the body regions and the drift regions to be extended into the wafer at least partially under the gate structure.  
   
   
       66 . The method according to  claim 65 , wherein, subsequent to the inclined ion implantation, a heat treatment is applied to the substrate to permit a further diffusion and activation of the drift and body regions.  
   
   
       67 . The method according to  claim 66 , wherein the heat treatment is applied at a temperature of less than 1000° C.  
   
   
       68 . The method according to  claim 67 , wherein the masking and further masking comprise forming photoresists and irradiating with electromagnetic waves through a corresponding photomask.  
   
   
       69 . The method according to  claim 68 , wherein the at least one LDMOS transistor comprises an N-channel LDMOS transistor and a P-channel LDMOS transistor; and wherein the N-channel transistor and P-channel transistor are both produced by inclined ion implantation through the first aperture and through the second aperture.  
   
   
       70 . The method according to  claim 58 , wherein the at least one LDMOS transistor comprises an N-channel LDMOS transistor and a P-channel LDMOS transistor.