Apparatus for increasing SRAM cell capacitance with metal fill

Abstract

A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an upper surface and a contact surface formed at the upper surface of the structure. A dielectric material is formed over the contact surface with a first conductive node and a second conductive node extending beyond the dielectric material. Dielectric spacers are formed around the first and second conductive nodes and conductive elements are formed between the dielectric spacers. The conductive elements and spacers form capacitors without implementing additional masking steps.

1 . A static random access memory cell comprising: 
 a first conductive element defining a first conductive node of the SRAM cell;    a second conductive element defining a second conductive node of the SRAM cell;    a first dielectric spacer disposed about a portion of the first conductive element;    a second dielectric spacer disposed about a portion of the second conductive element;    a first conductor disposed between the respective dielectric spacers of the first conductive element and the second conductive element;    a second conductor disposed adjacent the first conductive spacer opposite the second conductive element; and    a third conductor disposed adjacent the second dielectric spacer opposite the first conductive element.    
   
   
       2 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first dielectric spacer and the second dielectric spacer is between 50 angstroms and 500 angstroms in depth.  
   
   
       3 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first dielectric spacer and the second dielectric spacer is between 75 angstroms and 200 angstroms in depth.  
   
   
       4 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first dielectric spacer and the second dielectric spacer comprises an oxide.  
   
   
       5 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first dielectric spacer and the second dielectric spacer comprises a nitride.  
   
   
       6 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first conductor, the second conductor, and the third conductor comprises a tungsten material.  
   
   
       7 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first dielectric spacer and the second dielectric spacer is between 50 angstroms and 500 angstroms in width.  
   
   
       8 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first dielectric spacer and the second dielectric spacer is between 75 angstroms and 200 angstroms in width.  
   
   
       9 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first conductor, the second conductor and the third conductor comprises metal.  
   
   
       10 . The static random access memory cell, as set forth in  claim 1 , comprising a dielectric layer disposed over each of the first dielectric spacer, the second dielectric spacer, the first conductor, the second conductor and the third conductor.  
   
   
       11 . The static random access memory cell, as set forth in  claim 1 , wherein each of the first conductor, the second conductor and the third conductor comprises a capacitor.  
   
   
       12 . A memory device comprising: 
 a plurality of conductive contacts;    a dielectric layer disposed between each of the plurality of conductive contacts and about a lower portion of each of the plurality of conductive contacts;    dielectric spacers disposed about an upper portion of each of the plurality of conductive contacts; and    a respective metal fill region disposed between each of the dielectric spacers and adjacent to the upper portion of each of the plurality of conductive contacts.    
   
   
       13 . A system comprising: 
 a processor;    a memory sub-system operatively coupled to the processor and comprising at least one memory device having at least one static random access memory cell, wherein the at least one static random access memory cell comprises:    a first conductive element defining a first conductive node of the SRAM cell;    a second conductive element defining a second conductive node of the SRAM cell;    a first dielectric spacer disposed about a portion of the first conductive element;    a second dielectric spacer disposed about a portion of the second conductive element;    a first conductor disposed between the respective dielectric spacers of the first conductive element and the second conductive element;    a second conductor disposed adjacent the first conductive spacer opposite the second conductive element; and    a third conductor disposed adjacent the second dielectric spacer opposite the first conductive element.    
   
   
       14 . The system, as set forth in  claim 13 , wherein each of the first dielectric spacer and the second dielectric spacer is between 50 angstroms and 500 angstroms in depth.  
   
   
       15 . The system, as set forth in  claim 13 , wherein each of the first dielectric spacer and the second dielectric spacer is between 75 angstroms and 200 angstroms in depth.  
   
   
       16 . The system, as set forth in  claim 13 , wherein each of the first conductor, the second conductor, and the third conductor comprises a tungsten material.  
   
   
       17 . The system, as set forth in  claim 13 , wherein each of the first dielectric spacer and the second dielectric spacer is between 50 angstroms and 500 angstroms in width.  
   
   
       18 . The system, as set forth in  claim 13 , wherein each of the first dielectric spacer and the second dielectric spacer is between 75 angstroms and 200 angstroms in width.  
   
   
       19 . The system, as set forth in  claim 13 , wherein each of the first conductor, the second conductor, and the third conductor comprises metal.  
   
   
       20 . The system, as set forth in  claim 13 , comprising a dielectric layer disposed over each of the first dielectric spacer, the second dielectric spacer, the first conductor, the second conductor, and the third conductor.