Semiconductor device and methods of manufacturing the same

Abstract

A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

1 - 10 . (canceled)  
   
   
       11 . A semiconductor device comprising: 
 a semiconductor substrate having a uniform conductivity;    a PMOS transistor that includes a gate pattern composed of a gate oxide film and a gate conductive layer on a PMOS transistor region of the semiconductor substrate, ion-implanted low concentration source/drain regions formed on both sides of the gate pattern on the semiconductor substrate, and ion-implanted high concentration source/drain regions also formed on both sides of the gate pattern but at a distance far from the gate pattern; and    an NMOS transistor that includes a gate pattern composed of a gate oxide film and a gate conductive layer on an NMOS transistor region of the semiconductor substrate, ion-implanted low concentration source/drain regions formed on both sides of the gate pattern on the semiconductor substrate, and ion-implanted high concentration source/drain regions also formed on both sides of the gate pattern but at a distance relatively nearer to the gate pattern compared to the distance between the high concentration source/drain regions and the gate pattern of the PMOS transistor.    
   
   
       12 . A semiconductor device comprising: 
 a semiconductor substrate having a uniform conductivity; and    a PMOS transistor that includes a gate pattern composed of a gate oxide film and a gate conductive layer on a PMOS transistor region of the semiconductor substrate, a gate spacer on both sidewalls of the gate pattern, ion-implanted low concentration source/drain regions formed on both sides of the gate pattern in the semiconductor substrate, and ion-implanted high concentration source/drain regions also formed on both sides of the gate pattern but away from the gate spacer.    
   
   
       13 . (canceled)  
   
   
       14 . A semiconductor device characterized by a low concentration source/drain regions formed by using a gate pattern as an implant mask, a dielectric film formed on an entire upper part of a semiconductor substrate on which gate spacers are formed on both side walls of the gate pattern, and high concentration source/drain regions formed by using the dielectric film as an implant mask.