Solid-state high power device and method
Abstract
A high-power solid-state transistor structure comprised of a plurality of emitter or gate fingers in a uniform or non-uniform manner to provide improved high power performance is disclosed. Preferably, each of the fingers is associated with a corresponding one of a plurality of sub-cells, the sub-cells being arranged in at least one row. The advantage of the invention is that the structure can be practically implemented and the absolute thermal stability can be maintained for very high power transistors with reduced adverse effects resulting from random variation in the manufacturing and design process.
Claims
exact text as granted — not AI-modified1 . A high power transistor comprising:
a base, an emitter, a collector, and a plurality of elongated emitter fingers extending from and electrically connected to the emitter; wherein the elongated emitter fingers are arranged side by side in a row, the row extending between a first row end and a second row end and having a row center located at the midpoint between the first row end and the second row end; wherein the plurality of elongated emitter fingers includes a first pair of emitter fingers separated by a first side-to-side distance, and a second pair of emitter fingers separated by a second side-to-side distance, wherein the midpoint between the first pair of emitter fingers is positioned closer to the row center than the midpoint between the second pair of emitter fingers, and wherein the first side-to-side distance is greater than the second side-to-side distance; and further comprising at least one small ballast resistor having a value of less than about 10 ohms and electrically connected in series with at least one elongated emitter finger in the plurality of emitter fingers.
2 . The device of claim 1 , wherein the value of the at least one small ballast resistor is less than about 5 ohms.
3 . The device of claim 1 , wherein the first side-to-side distance is at least twice as big as the second side-to-side distance.
4 . The device of claim 1 , wherein the at least one small ballast resistor is formed using a contact hole through a passivation layer to an emitter metal layer, wherein the contact hole has dimensions less than about 1 micron by 1 micron.
5 . The device of claim 1 , wherein the base includes a layer of GaAs, and wherein the width of at least one elongated emitter finger is less than about 1.2 microns.
6 . The device of claim 1 , wherein the base includes a layer of GaAs, and wherein the width of at least one elongated emitter finger is about 0.8 microns.
7 . The device of claim 1 , wherein the base includes a layer of GaAs, and wherein the thickness of the layer of GaAs is less than about 100 microns.
8 . The device of claim 1 , wherein the base includes a layer of GaAs, and wherein the thickness of the layer of GaAs is about 80 microns.
9 . The device of claim 1 , wherein the base includes a layer of GaAs, wherein the majority of the elongated emitter fingers have widths that are less than about 1.2 microns.
10 . The device of claim 9 , wherein the thickness of the layer of GaAs is less than about 100 microns.
11 . A high power transistor comprising:
a base, an emitter, a collector, and a plurality of emitter finger subcells, each emitter finger subcell comprising one or more elongated emitter fingers extending from and electrically connected to the emitter; wherein the emitter finger subcells are arranged side by side in a row, the row extending between a first row end and a second row end and having a row center located at the midpoint between the first row end and the second row end; wherein the plurality of emitter finger subcells includes a first pair of emitter finger subcells separated by a first side-to-side distance, and a second pair of emitter finger subcells separated by a second side-to-side distance, wherein the midpoint between the first pair of emitter finger subcells is positioned closer to the row center than the midpoint between the second pair of emitter finger subcells, and wherein the first side-to-side distance is greater than the second side-to-side distance; and further comprising at least one small ballast resistor having a value of less than about 10 ohms and electrically connected in series with at least one elongated emitter finger in the plurality of emitter finger subcells.
12 . The device of claim 11 , wherein each emitter finger subcell includes at least two elongated emitter fingers.
13 . The device of claim 11 , wherein the first side-to-side distance is at least twice as big as the second side-to-side distance.
14 . The device of claim 11 , wherein the at least one small ballast resistor is formed using a contact hole through a passivation layer to an emitter metal layer, wherein the contact hole has dimensions less than about 1 micron by 1 micron.
15 . The device of claim 11 , wherein the base includes a layer of GaAs, and wherein the width of at least one elongated emitter finger is less than about 1.2 microns.
16 . The device of claim 11 , wherein the base includes a layer of GaAs, and wherein the width of at least one elongated emitter finger is about 0.8 microns.
17 . The device of claim 11 , wherein the base includes a layer of GaAs, and wherein the thickness of the layer of GaAs is less than about 100 microns.
18 . The device of claim 11 , wherein the plurality of emitter finger subcells includes a first subcell and a second subcell, wherein the first subcell is positioned closer to the row center than the second subcell, and wherein the number of elongated emitter fingers in the first subcell is less than the number of elongated emitter fingers in the second subcell.
19 . The device of claim 18 , wherein the number of elongated emitter fingers in the first subcell is one.
20 . The device of claim 11 , wherein the wherein the plurality of emitter finger subcells includes a first subcell and a second subcell, wherein the first subcell is positioned closer to the row center than the second subcell, and wherein the area of the elongated emitter fingers in the first subcell is less than the area of the elongated emitter fingers in the second subcell.
21 . A high power transistor comprising:
a base, an emitter, a collector, and a plurality of elongated emitter fingers extending from and electrically connected to the emitter; wherein the elongated emitter fingers are arranged side by side in a plurality of rows, each row extending between a first row end and a second row end and having a row center located at the midpoint between the first row end and the second row end; wherein the plurality of elongated emitter fingers in at least one row in the plurality of rows includes a first pair of emitter fingers separated by a first side-to-side distance, and a second pair of emitter fingers separated by a second side-to-side distance, wherein the midpoint between the first pair of emitter fingers is positioned closer to the row center than the midpoint between the second pair of emitter fingers, and wherein the first side-to-side distance is greater than the second side-to-side distance; and further comprising at least one small ballast resistor having a value of less than about 10 ohms and electrically connected in series with at least one elongated emitter finger in the plurality of emitter fingers.
22 . The device of claim 21 , wherein the value of the at least one small ballast resistor is less than about 5 ohms.
23 . The device of claim 21 , wherein the first side-to-side distance is at least twice as big as the second side-to-side distance.
24 . The device of claim 21 , wherein the at least one small ballast resistor is formed using a contact hole through a passivation layer to an emitter metal layer, wherein the contact hole has dimensions less than about 1 micron by 1 micron.
25 . The device of claim 21 , wherein the base includes a layer of GaAs, and wherein the width of at least one elongated emitter finger is less than about 1.2 microns.
26 . The device of claim 21 , wherein the base includes a layer of GaAs, and wherein the width of at least one elongated emitter finger is about 0.8 microns.
27 . The device of claim 21 , wherein the base includes a layer of GaAs, and wherein the thickness of the layer of GaAs is less than about 100 microns.
28 . The device of claim 21 , wherein the base includes a layer of GaAs, and wherein the thickness of the layer of GaAs is about 80 microns.
29 . The device of claim 21 , wherein the base includes a layer of GaAs, wherein the majority of the elongated emitter fingers have widths that are less than about 1.2 microns.
30 . The device of claim 29 , wherein the thickness of the layer of GaAs is less than about 100 microns.
31 . A high power transistor comprising:
a base, an emitter, a collector, and a plurality of emitter finger subcells, each emitter finger subcell comprising one or more elongated emitter fingers extending from and electrically connected to the emitter; wherein the emitter finger subcells are arranged side by side in a plurality of rows, each row extending between a first row end and a second row end and having a row center located at the midpoint between the first row end and the second row end; wherein the plurality of emitter finger subcells in at least one row in the plurality of rows includes a first pair of emitter finger subcells separated by a first side-to-side distance, and a second pair of emitter finger subcells separated by a second side-to-side distance, wherein the midpoint between the first pair of emitter finger subcells is positioned closer to the row center than the midpoint between the second pair of emitter finger subcells, and wherein the first side-to-side distance is greater than the second side-to-side distance; and further comprising at least one small ballast resistor having a value of less than about 10 ohms and electrically connected in series with at least one elongated emitter finger in the plurality of emitter finger subcells.
32 . The device of claim 31 , wherein each emitter finger subcell includes at least two elongated emitter fingers.
33 . The device of claim 31 , wherein the first side-to-side distance is at least twice as big as the second side-to-side distance.
34 . The device of claim 31 , wherein the plurality of rows includes a first row and a second row;
wherein the distance between the row center of the first row and the row center of the second row is greater than the distance between the first row end of the first row and the first row end of the second row; and wherein the distance between the row center of the first row and the row center of the second row is greater than the distance between the second row end of the first row and the second row end of the second row.
35 . The device of claim 34 , wherein the plurality of rows further comprises a third row, wherein the third row is positioned between the first row and the second row, and wherein the third row is substantially straight.
36 . The device of claim 31 , wherein the base includes a layer of GaAs, and wherein the width of at least one elongated emitter finger is less than about 1.2 microns.
37 . The device of claim 31 , wherein the base includes a layer of GaAs, and wherein the thickness of the layer of GaAs is less than about 100 microns.
38 . The device of claim 31 , wherein the plurality of emitter finger subcells in at least one row in the plurality of rows includes a first subcell and a second subcell, wherein the first subcell is positioned closer to the row center than the second subcell, and wherein the number of elongated emitter fingers in the first subcell is zero or more and less than the number of elongated emitter fingers in the second subcell.
39 . The device of claim 38 , wherein the number of elongated emitter fingers in the first subcell is one or more.
40 . The device of claim 31 , wherein the plurality of emitter finger subcells in at least one row includes a first subcell and a second subcell, wherein the first subcell is positioned closer to the row center than the second subcell, and wherein the area of the elongated emitter fingers in the first subcell is less than the area of the elongated emitter fingers in the second subcell.Join the waitlist — get patent alerts
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