Method and apparatus for managing the configuration and functionality of a semiconductor design

Abstract

A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

1 - 51 . (canceled)  
     
     
         52 . A computer-implemented method of producing at least a portion of an integrated circuit design, said design including at least one of a processor or processor peripheral device, the method comprising the following acts performed by a computer process: 
 receiving one or more inputs from a user for at least one customized parameter of the processor or processor peripheral;    generating a customized description language model based on the least one customized parameter, said act of generating including the act of modifying at least one prototype description by substituting or modifying values in the at least one prototype description, or merging additional descriptions based on the at least one customized parameter; and    generating test code associated with the customized description language model based at least in part on the at least one customized parameter;    wherein the customized description language model includes both functional and structural description language elements for the processor or processor peripheral.    
     
     
         53 . The method of  claim 52 , wherein said act of merging additional descriptions comprises merging at least one extension comprising a predetermined logical function.  
     
     
         54 . The method of  claim 52 , wherein said act of merging additional descriptions comprises merging at least one custom instruction.  
     
     
         55 . The method of  claim 52 , wherein said one or more inputs comprise at least one input selected from the group consisting of (i) overall device or system configuration, (ii) width of the external memory system data bus, and (iii) cache type/size.  
     
     
         56 . The method of  claim 52 , wherein said act of generating test code comprises generating configuration register test code.  
     
     
         57 . The method of  claim 52 , wherein said act of generating test code comprises generating test code based at least in part on one or more extensions added to said customized description language model as part of said act of generating said model.  
     
     
         58 . The method of  claim 52 , wherein said processor or processor peripheral comprises a RISC processor, and said description language model comprises a VHDL model.  
     
     
         59 . The method of  claim 58 , further comprising causing a first computer program to write a second computer program adapted to perform a specific task based at least in part on said user inputs during said act of generating a customized description language model.  
     
     
         60 . The method of  claim 59 , further comprising executing said second program to perform said task.  
     
     
         61 . The method of  claim 52 , further comprising evaluating the acceptability of said description language model using at least said test code.  
     
     
         62 . The method of  claim 52 , further comprising testing the customized description language through simulation or synthesis using said test code; and 
 if a different testing outcome is desired, receiving one or more additional inputs and generating a second customized description language model.    
     
     
         63 . The method of  claim 52 , wherein the method further comprises conducting a hardware/software co-verification.  
     
     
         64 . The method of  claim 63 , wherein the act of conducting a hardware/software co-verification further comprises using a debugger to run software using at least a portion of the description language model.  
     
     
         65 . The method of  claim 52 , wherein the method further comprises conducting a core verification as part of the act of generating a customized description language model.  
     
     
         66 . Apparatus configured to produce at least a portion of an integrated circuit design, said design including at least one of a processor or processor peripheral device, the apparatus having at least one computer program comprising: 
 a first module adapted to receive one or more inputs from a user for at least one customized parameter of the processor or processor peripheral;    a second module adapted to generate a customized description language model based on the least one customized parameter, said generating of said model including modifying at least one prototype description by substituting or modifying values in the at least one prototype description, or merging additional descriptions based on the at least one customized parameter; and    a third module adapted for automated generation of test code associated with the customized description language model based at least in part on the at least one customized parameter;    wherein the customized description language model includes both functional and structural description language elements for the processor or processor peripheral.    
     
     
         67 . The apparatus of  claim 66 , wherein said apparatus further comprises a processor, display device, internal memory, and input device.  
     
     
         68 . The apparatus of  claim 66 , wherein said one or more inputs comprise at least one input selected from the group consisting of (i) overall device or system configuration, (ii) width of the external memory system data bus, and (iii) cache type/size.  
     
     
         69 . The apparatus  claim 66 , wherein said test code comprises configuration register test code.  
     
     
         70 . The apparatus of  claim 66 , wherein said test code is generated based at least in part on one or more extensions added to said customized description language model as part of said act of generating said model.  
     
     
         71 . The apparatus of  claim 66 , wherein said processor or processor peripheral comprises a RISC processor, and said description language model comprises a VHDL model.  
     
     
         72 . The apparatus of  claim 66 , further comprising a first computer program which writes a second computer program adapted to perform a specific task based at least in part on said user inputs.  
     
     
         73 . The apparatus of  claim 72 , wherein said apparatus further automatically executes said second program to perform said task.  
     
     
         74 . The apparatus of  claim 66 , further comprising a module configured to evaluate the acceptability of said description language model using at least said test code.  
     
     
         75 . The apparatus of  claim 66 , further comprising a module adapted to test the customized description language through simulation or synthesis using said test code; 
 wherein if a different testing outcome is desired, said apparatus is further configured to receive one or more additional inputs and cause generation of a second customized description language model.    
     
     
         76 . The apparatus of  claim 66 , further comprising a module adapted to conduct a hardware/software co-verification.  
     
     
         77 . The apparatus of  claim 76 , wherein the act of conducting a hardware/software co-verification further comprises using a debugger to run software using at least a portion of the description language model.  
     
     
         78 . The apparatus of  claim 66 , further comprising a module adapted to conduct a core verification as part of the generation of said customized description language model.  
     
     
         79 . A computer-implemented method of generating a hardware description language (HDL) model of an integrated circuit design, said design including at least one of a processor or processor peripheral device, the method comprising the following acts performed by a computer process: 
 receiving one or more inputs from a user for at least one customized parameter of the processor or processor peripheral;    generating a customized description language model based on the least one customized parameter, said act of generating including the act of modifying at least one prototype description by substituting or modifying values in the at least one prototype description, or merging additional descriptions based on the at least one customized parameter; and    generating test code associated with the customized description language model based at least in part on the at least one customized parameter;    wherein the customized description language model includes both functional and structural description language elements for the processor or processor peripheral;    wherein said act of merging additional descriptions comprises merging at least one custom instruction; and    wherein said act of generating test code comprises generating test code based at least in part on one or more extensions added to said customized description language model.    
     
     
         80 . The method of  claim 79 , wherein said acts of generating both comprise generating via an automated process.  
     
     
         81 . The method of  claim 80 , wherein said one or more inputs comprise at least one input selected from the group consisting of (i) overall device or system configuration, (ii) width of the external memory system data bus, and (iii) cache type/size.  
     
     
         82 . The method of  claim 80 , wherein said act of generating test code comprises generating configuration register test code.  
     
     
         83 . The method of  claim 80 , wherein said processor or processor peripheral-comprises a RISC processor, and said description language model comprises a VHDL model.  
     
     
         84 . The method of  claim 80 , further comprising causing a first computer program to write a second computer program adapted to perform a specific task based at least in part on said user inputs during said act of generating a customized description language model.  
     
     
         85 . The method of  claim 84 , further comprising executing said second program to perform said task.  
     
     
         86 . The method of  claim 79 , further comprising evaluating the acceptability of said description language model using at least said test code.  
     
     
         87 . The method of  claim 79 , further comprising testing the customized description language through simulation or synthesis using said test code; and 
 if a different testing outcome is desired, receiving one or more additional inputs and generating a second customized description language model.    
     
     
         88 . The method of  claim 79 , wherein the method further comprises conducting a hardware/software co-verification.  
     
     
         89 . The method of  claim 88 , wherein the act of conducting a hardware/software co-verification further comprises using a debugger to run software using at least a portion of the description language model.  
     
     
         90 . The method of  claim 80 , wherein the method further comprises conducting a core verification as part of the act of generating a customized description language model.  
     
     
         91 . A method of producing at least a portion of an integrated circuit design, said design including at least one of a processor or processor peripheral device, the method comprising: 
 receiving one or more user inputs for at least one configuration parameter of the processor or processor peripheral;    generating a customized description language model based on the least one configuration parameter, said act of generating including the act of modifying at least one of an existing description by substituting or modifying values in the at least one existing description; and    generating test code associated with the customized description language model;    wherein the customized description language model includes both functional and structural elements for the processor or processor peripheral.    
     
     
         92 . The method of  claim 91 , wherein said functional and structural elements comprise functional description language elements and structural description language elements, respectively.  
     
     
         93 . The method of  claim 91 , wherein said act of substituting or modifying comprises merging at least one additional description based on the at least one configuration parameter.  
     
     
         94 . The method of  claim 91 , wherein said method is performed interactively using a computer program.  
     
     
         95 . The method of  claim 94 , wherein said act of receiving comprises selecting at least one extension for inclusion within said design, said at least one extension being selected before said act of generating a customized description language model is performed.  
     
     
         96 . The method of  claim 91 , wherein said act of receiving comprises selecting at least one extension for inclusion within said design.  
     
     
         97 . The method of  claim 96 , wherein said at least one extension is selected before said act of generating a customized description language model is performed.  
     
     
         98 . The method of  claim 93 , wherein said act of merging at least one additional description comprises merging at least one extension comprising a predetermined logical function.  
     
     
         99 . The method of  claim 93 , wherein said act of merging additional descriptions comprises merging at least one custom instruction.  
     
     
         100 . The method of  claim 91 , wherein said one or more inputs comprise at least one input selected from the group consisting of (i) overall device or system configuration, (ii) width of the external memory system data bus, and (iii) cache type/size.  
     
     
         101 . The method of  claim 91 , wherein said act of generating test code comprises generating configuration register test code.  
     
     
         102 . The method of  claim 91 , wherein said act of generating test code comprises generating test code based at least in part on one or more extensions added to said customized description language model as part of said act of generating said model.  
     
     
         103 . The method of  claim 91 , further comprising causing a first computer program to write a second computer program adapted to perform a specific task based at least in part on said user inputs during said act of generating a customized description language model.  
     
     
         104 . The method of  claim 103 , further comprising executing said second program to perform said task.  
     
     
         105 . The method of  claim 91 , further comprising evaluating the acceptability of said description language model using at least said test code.  
     
     
         106 . The method of  claim 91 , further comprising testing the customized description language through simulation or synthesis using said test code; and 
 if a different testing outcome is desired, receiving one or more additional inputs and generating a second customized description language model.    
     
     
         107 . The method of  claim 91 , wherein the method further comprises conducting a hardware/software co-verification.  
     
     
         108 . The method of  claim 107 , wherein the act of conducting a hardware/software co-verification further comprises using a debugger to run software using at least a portion of the description language model.  
     
     
         109 . Apparatus configured to produce at least a portion of an integrated circuit design, said design including at least one of a processor or processor peripheral device, the apparatus having at least one computer program comprising: 
 a first module adapted to receive one or more user inputs for at least one customized parameter of the processor or processor peripheral;    a second module adapted to generate a customized description language model based on the least one customized parameter, said generating of said model including modifying at least one existing description by substituting or modifying values in the at least one existing description; and    a third module adapted for automated generation of test code associated with the customized description language model;    wherein the customized description language model includes both functional and structural elements for the processor or processor peripheral.    
     
     
         110 . The apparatus of  claim 109 , wherein said functional and structural elements comprise functional description language elements and structural description language elements, respectively.  
     
     
         111 . The apparatus of  claim 109 , wherein said substituting or modifying comprises merging at least one additional description based on the at least one configuration parameter.  
     
     
         112 . The apparatus of  claim 109 , wherein said first module is further adapted to receive a user selection of at least one extension for inclusion within said design, said at least one extension being selected before said act of generating a customized description language model is performed.  
     
     
         113 . The apparatus of  claim 109 , wherein said apparatus further comprises a processor, display device, internal memory, and input device.  
     
     
         114 . The apparatus of  claim 109 , wherein said one or more inputs comprise at least one input selected from the group consisting of (i) overall device or system configuration, (ii) width of the external memory system data bus, and (iii) cache type/size.  
     
     
         115 . The apparatus  claim 109 , wherein said test code comprises configuration register test code.  
     
     
         116 . The apparatus of  claim 109 , wherein said processor or processor peripheral comprises a RISC processor, and said description language model comprises a VHDL model.  
     
     
         117 . The apparatus of  claim 109 , further comprising a second computer program which writes a third computer program adapted to perform a specific task based at least in part on said user inputs.  
     
     
         118 . The apparatus of  claim 117 , wherein said second computer program is integrated with said computer program, and said third program is automatically executed to perform said task.  
     
     
         119 . The apparatus of  claim 109 , further comprising a module configured to evaluate the acceptability of said description language model using at least said test code.  
     
     
         120 . The apparatus of  claim 109 , further comprising a module adapted to test the customized description language through simulation or synthesis using said test code; 
 wherein if a different testing outcome is desired, said apparatus is further configured to receive one or more additional inputs and cause generation of a second customized description language model.    
     
     
         121 . The apparatus of  claim 109 , further comprising a module adapted to conduct a hardware/software co-verification.  
     
     
         122 . The apparatus of  claim 121 , wherein the act of conducting a hardware/software co-verification further comprises using a debugger to run software using at least a portion of the description language model.  
     
     
         123 . The apparatus of  claim 109 , further comprising a module adapted to conduct a core verification as part of the generation of said customized description language model.  
     
     
         124 . Storage apparatus, comprising: 
 storage media configured to store at least one computer program; and    at least one computer program stored on said media and configured to produce at least a portion of an integrated circuit design, said design including at least one of a processor or processor peripheral device, the at least one computer program comprising:    a first module adapted to receive one or more user inputs for at least one customized parameter of the processor or processor peripheral;    a second module adapted to generate a customized description language model having both structural and functional elements and based on the least one customized parameter, said generation of said model including modification of at least one existing description by substituting or modifying values in the at least one existing description; and    a third module adapted for automated generation of test code associated with the customized description language model.    
     
     
         125 . A method of enabling the generation of at least a portion of an integrated circuit design, comprising: 
 providing at least one computer program stored on said media and configured to produce at least a portion of an integrated circuit design, said design including at least one of a processor or processor peripheral device, the at least one computer program comprising:    a first module adapted to receive one or more user inputs for at least one customized parameter of the processor or processor peripheral;    a second module adapted to generate a customized description language model having both structural and functional elements and based on the least one customized parameter, said generation of said model including modification of at least one existing description by substituting or modifying values in the at least one existing description; and    a third module adapted for automated generation of test code associated with the customized description language model; and    enabling said computer program so that it may be operated on a computerized device.