Scoreboarding mechanism in a pipeline that includes replays and redirects

Abstract

An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.

1 - 17 . (canceled)  
   
   
       18 . A method comprising: 
 updating a first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline;    updating a second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline, wherein replay is signaled at the first stage; and    in response to a replay of a second instruction, copying a contents of the second scoreboard to the first scoreboard.    
   
   
       19 . The method as recited in  claim 18  further comprising: 
 updating a third scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a second stage of the pipeline, wherein an instruction graduates at the second stage; and    in response to an exception for a third instruction, copying a contents of the third scoreboard to the second scoreboard and to the first scoreboard.    
   
   
       20 . The method as recited in  claim 19  wherein the copying the contents of the third scoreboard comprises: 
 copying the contents of the third scoreboard to the second scoreboard; and    subsequently copying a contents of the second scoreboard to the first scoreboard.    
   
   
       21 . The method as recited in  claim 18  further comprising: 
 detecting a redirect due to a mispredicted branch instruction at the first stage; and    in response to the redirect, copying the contents of the second scoreboard to the first scoreboard.    
   
   
       22 . The method as recited in  claim 18  further comprising detecting the replay of the second instruction by checking operands of the second instruction against the second scoreboard.  
   
   
       23 . The method as recited in  claim 18  wherein the first scoreboard and the second scoreboard track pending writes to integer registers.  
   
   
       24 . The method as recited in  claim 23  further comprising selectively inhibiting issuance of a third instruction dependent on which of a plurality of pipelines to which the third instruction is to be issued if the first scoreboard indicates a write pending to one of the operands of the third instruction.  
   
   
       25 - 33 . (canceled)