CMOS performance enhancement using localized voids and extended defects

Abstract

The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

1 - 20 . (canceled)  
   
   
       21 . An integrated circuit comprising: 
 a P-type field effect transistor (PFET) having a source and a drain implanted with a substance that produces a compressive stress in a body of the PFET.    
   
   
       22 . An integrated circuit according to  claim 21 , wherein the compressive stress is on a gate channel region of the PFET.  
   
   
       23 . An integrated circuit according to  claim 21 , wherein said substance is Ge.  
   
   
       24 . An integrated circuit according to  claim 23 , wherein the PFET is formed in a silicon substrate, so that SiGe is formed in the source and the drain.  
   
   
       25 . An integrated circuit according to  claim 24 , wherein the formation of SiGe by the implant causes formation of extended extrinsic defects in the source and the drain.  
   
   
       26 . An integrated circuit according to  claim 21 , further comprising an N-type field effect transistor (NFET) having a tensile stress on a body thereof.  
   
   
       27 . An integrated circuit comprising: 
 A p-type field effect transistor (PFET) in a silicon substrate, the PFET having a source and a drain implanted with ge, whereby SiGe is formed in the source and the drain and a compressive stress is produced in a body of the PFET.    
   
   
       28 . An integrated circuit according to  claim 27 , wherein the compressive stress is on a gate channel region of the PFET.  
   
   
       29 . An integrated circuit according to  claim 27 , wherein the compressive stress is produced as a result of formation of SiGe by the implant and subsequent annealing to form extended extrinsic defects in the source and the drain.  
   
   
       30 . An integrated circuit according to  claim 27 , further comprising an N-type field effect transistor (NFET) having a tensile stress on a body thereof.