Method for fabricating a flash-preventing window ball grid array semiconductor package

Abstract

A flash-preventing window ball grid array semiconductor package, a method for fabricating the same, and a chip carrier used in the semiconductor package are provided. The chip carrier has a through hole and has a surface formed with a plurality of wire-bonding portions, ball-bonding portions and intended-exposing regions. A chip is mounted over the through hole and electrically connected to the wire-bonding portions by a plurality of bonding wires penetrating through the through hole. An encapsulation body encapsulates the chip and bonding wires. The intended-exposing regions serve as a narrow runner which is filled with an encapsulating material forming the encapsulation body, making the encapsulating material not flash over the ball-bonding portions. This allows a plurality of solder balls to be well bonded to the ball-bonding portions, thereby assuring the quality of electrical connection and the surface planarity of the semiconductor package.

1 . A method for fabricating a window ball grid array (WBGA) semiconductor package, comprising the steps of: 
 preparing a core layer, the core layer having a first surface and an opposite second surface, and a through hole penetrating through the core layer, wherein the second surface is formed with a plurality of wire-bonding portions around the through hole, a plurality of ball-bonding portions, and a plurality of intended-exposing regions around the wire-bonding portions;    applying a solder mask layer over the second surface of the core layer while exposing the ball-bonding portions, wherein the solder mask layer is formed with an opening for exposing the through hole, the wire-bonding portions, and the intended-exposing regions;    preparing at least one chip which is mounted on the first surface of the core layer and over the through hole, with a portion of the chip exposed via the through hole;    forming a plurality of bonding wires which penetrate through the through hole and electrically connect the chip to the wire-bonding portions;    performing a molding process to form a first encapsulation body on the first surface of the core layer to encapsulate the chip, and a second encapsulation body on the second surface of the core layer to encapsulate the bonding wires, wherein the intended-exposing regions serve as a narrow runner for an encapsulating material forming the second encapsulation body; and    depositing a plurality of solder balls on the ball-bonding portions.    
     
     
         2 . The method of  claim 1 , wherein a width of the intended-exposing region is of a range from 0.2 to 0.8 mm.  
     
     
         3 . The method of  claim 2 , wherein the width of the intended-exposing region is 0.4 mm.  
     
     
         4 . The method of  claim 1 , wherein the intended-exposing regions are located adjacent to the wire-bonding portions.  
     
     
         5 . The method of  claim 1 , wherein the opening of the solder mask layer is larger in width than a mold cavity of a mold used for forming the second encapsulation body.  
     
     
         6 . The method of  claim 1 , wherein the encapsulating material forming the second encapsulation body is filled in the narrow runner to allow the second encapsulation body covering the intended-exposing regions to have a thickness substantially equal to that of the solder mask layer.  
     
     
         7 . The method of  claim 1 , further comprising: applying a layer of patterned conductive traces between the second surface of the core layer and the solder mask layer.  
     
     
         8 . The method of  claim 1 , further comprising: applying another solder mask layer between the first surface of the core layer and the chip.  
     
     
         9 - 20 . (canceled)