System having two or more packet interfaces, a switch, and a shared packet DMA circuit

Abstract

An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

1 . An apparatus comprising: 
 a first interface circuit configured to couple to a first interface for receiving and transmitting packet data;    a second interface circuit configured to couple to a second interface for receiving and transmitting packet data;    a memory controller configured to interface to a memory; and    a packet direct memory access (DMA) circuit coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit, wherein the packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory.    
   
   
       2 . The apparatus as recited in  claim 1  wherein the packet DMA circuit is configured to generate read commands to read a third packet from the memory controller for transmission by the first interface circuit on the first interface and a fourth packet from the memory controller for transmission by the second interface circuit on the second interface.  
   
   
       3 . The apparatus as recited in  claim 1  wherein the first interface circuit, the second interface circuit, the memory controller, and the packet DMA circuit are integrated onto an integrated circuit.  
   
   
       4 . The apparatus as recited in  claim 1  wherein each of the first interface circuit and the second interface circuit is configurable to communicate on two or more interfaces.  
   
   
       5 . The apparatus as recited in  claim 4  wherein one of the two or more interfaces is a HyperTransport interface.  
   
   
       6 . The apparatus as recited in  claim 4  wherein one of the two or more interfaces is a system packet interface.  
   
   
       7 - 22 . (canceled)