Semiconductor switching devices

Abstract

A compact switching device for applications in semiconductor integrated circuits is disclosed. The switching device includes a conducting path of a first device between a first supply voltage and a common output, a conducting path of a second device between a second supply voltage and the common output, and a common input to control conduction in said first and second devices. Said first and second devices are constructed either as complementary IGFET devices or as Gated-FET devices or as mixed IGFET and Gated-FET devices. The conducting paths are constructed on very thin semiconductor films, and designed to comprise a fully depleted hub region for both N-type and P-type hub regions from the common input. Furthermore, the hub regions also contain full accumulation depths of majority carriers to enhance device characteristics. Due to these improved characteristics, the conducting paths of the first and second devices can merge to form a single geometry of said thin semiconductor film, facilitating constructions of very compact switches.

1 . A switching device in a semiconductor integrated circuit comprising: 
 a first device having a conducting path coupled between a first supply voltage and a common output, said device having a conductive and a non-conductive mode;    a second device having a conducting path coupled between a second supply voltage and said common output, said device having a conductive and a non-conductive mode; and    a common input to control the modes between conductive and non-conductive in said first and second devices;    wherein each of said conducting paths of the first and second devices comprises: 
 a very thin semiconductor material having a first thickness; and  
 a hub region designed to be fully depleted of majority carriers in said first thickness, said depletion created by a voltage level applied at said common input.  
   
     
     
         2 . The device in  claim 1 , wherein each of the hub regions is further designed to fully contain an entire majority carrier accumulation layer within said first thickness, said accumulation created by a voltage level applied at said common input.  
     
     
         3 . The device in  claim 1 , wherein said first thickness is within the range of 20 to 500 Angstroms, and preferably within the range of 50 to 400 Angstroms and more preferably within the range of 100 to 300 Angstroms.  
     
     
         4 . The device in  claim 1 , wherein said thin semiconductor material comprises one of a single crystal, a polycrystalline, a recrystallized, and a doped semiconductor thin film.  
     
     
         5 . The device in  claim 1 , wherein said thin semiconductor material comprises one of SOI (Silicon-on-Insulator) and thinned down SOI semiconductor film.  
     
     
         6 . The device in  claim 1  comprising a thin film transistor constructed in a plane substantially different from a wafer substrate plane used for logic circuitry transistor construction.  
     
     
         7 . The device in  claim 1 , wherein each of said conducting paths of the first and second devices further comprises: 
 a source region and a drain region, said hub region formed in between said source and drain regions, wherein the source region of the first device is coupled to said first supply voltage, and the source region of the second device is coupled to said second supply voltage, and the two drain regions are coupled to said common output;    a dielectric layer formed above said hub region; and    a gate region formed above said dielectric layer coupled to said common input, wherein a first voltage level at the common input makes the first device conductive and the second device non-conductive, and a second voltage level at the common input makes the first device non-conductive and the second device conductive.    
     
     
         8 . The device in  claim 7 , wherein conducting paths of the first and second devices merge at the drain regions to form a single geometry of said thin semiconductor film.  
     
     
         9 . The device in  claim 7 , wherein each of said first and second devices comprises an Insulated-Gate Field-Effect Transistor (IGFET) comprised of said hub region further comprising: 
 a floating body region having said first thickness and a dopant type opposite to said drain and source regions; and    a substantially conductive state wherein the surface in the body region is inverted and the rest of the body region is fully depleted of majority carriers by a voltage level at said common input; and    a substantially non-conductive state wherein the body region is accumulated with majority carriers beyond the intrinsic dopant level by a voltage level at said common input.    
     
     
         10 . The device in  claim 7 , wherein each of said first and second devices comprises a Gated Field-Effect Transistor (Gated-FET) comprised of said hub region further comprising: 
 a resistive channel region having said first thickness, and a lower level of the same dopant type as said drain and source regions; and    a substantially conductive state wherein the channel region is accumulated with majority carriers beyond the intrinsic dopant level by a voltage level at said common input; and    a substantially non-conductive state wherein the channel region is fully depleted of majority carriers by a voltage level at said common input.    
     
     
         11 . The device in  claim 7   claim 9  or  claim 10 , further comprising an inverter, wherein said first voltage level is the second supply voltage, and said second voltage level is the first supply voltage, and wherein: 
 the first voltage level at the input couples the first supply voltage to the output; and    the second voltage level at the input couples the second supply voltage to the output.    
     
     
         12 . A switching device in a semiconductor integrated circuit comprising: 
 a first supply voltage;    a second supply voltage at a voltage level lower than said first supply voltage;    a common input having a first voltage level, and a second voltage level lower than said first voltage level;    a common output;    a first device comprised of: 
 a conducting film, and a gate to modulate the conduction of said film, wherein said conducting film has a source region, a drain region, and a body region of opposite dopant type to said source and drain regions formed between said source and drain regions;  
 the source region coupled to said first supply voltage, the drain region coupled to said common output, and the gate coupled to said common input;  
 the body modulated between a non-conductive state and a conductive state by said first and second common input voltage levels respectively; and  
   a second device comprised of: 
 a conducting film, and a gate to modulate the conduction of said film, wherein said conducting film has a source region, a drain region, and a body region of opposite dopant type to said source and drain regions formed between said source and drain regions;  
 the source region coupled to said second supply voltage, the drain region coupled to said common output, and the gate coupled to said common input;  
 the body modulated between a conductive state and a non-conductive state by said first and second common input voltage levels respectively;  
   wherein said conducting films of first and second devices comprises a very thin semiconductor material having a first thickness; and    wherein each of said body regions is designed to contain a surface inversion layer and be fully depleted of majority carriers inside said first thickness to eliminate a floating body region during the conductive state.    
     
     
         13 . The device in  claim 12 , wherein said first thickness is within the range of 20 to 500 Angstroms, and preferably within the range of 50 to 400 Angstroms and more preferably within the range of 100 to 300 Angstroms.  
     
     
         14 . The device in  claim 12 , wherein said thin semiconductor material comprises one of a single crystal, a polycrystalline, a re-crystallized, and a doped semiconductor thin film.  
     
     
         15 . The device in  claim 12 , wherein conducting paths of the first and second devices merge at the drain regions to form a single geometry of said thin semiconductor film.  
     
     
         16 . A switching device in a semiconductor integrated circuit comprising: 
 a first supply voltage;    a second supply voltage at a voltage level lower than said first supply voltage;    a common input having a first voltage level, and a second voltage level lower than said first voltage level;    a common output;    a first device comprised of: 
 a conducting film, and a gate to modulate the conduction of said film, wherein said conducting film has a source region, a drain region, and a resistive channel region having a lower level of the same dopant type as said source and drain regions formed between said source and drain regions;  
 the source region coupled to said first supply voltage, the drain region coupled to said common output, and the gate coupled to said common input;  
 the resistive channel modulated between a non-conductive state and a conductive state by said first and second common input voltage levels respectively; and  
   a second device comprised of: 
 a conducting film, and a gate to modulate the conduction of said film, wherein said conducting film has a source region, a drain region, and a resistive channel region having a lower level of the same dopant type as said source and drain regions formed between said source and drain regions;  
 the source region coupled to said second supply voltage, the drain region coupled to said common output, and the gate coupled to said common input;  
 the resistive channel modulated between a conductive state and a non-conductive state by said first and second common input voltage levels respectively;  
   wherein said conducting films of first and second devices comprises a very thin semiconductor material having a first thickness; and    wherein each of said channel regions is designed to be fully depleted of majority carriers inside said first thickness during the non-conductive state.    
     
     
         17 . The device in  claim 16 , wherein each of said channel regions is further designed to contain an accumulation of majority carriers beyond the level of intrinsic doping within said first thickness during the conductive state.  
     
     
         18 . The device in  claim 16 , wherein said first thickness is within the range of 20 to 500 Angstroms, and preferably within the range of 50 to 400 Angstroms and more preferably within the range of 100 to 300 Angstroms.  
     
     
         19 . The device in  claim 16 , wherein said thin semiconductor material comprises one of a single crystal, a polycrystalline, a re-crystallized, and a doped semiconductor thin film.  
     
     
         20 . The device in  claim 16 , wherein conducting paths of the first and second devices merge at the drain regions to form a single geometry of said thin semiconductor film.