Spacer integration scheme in MRAM technology

Abstract

A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

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       11 . A magnetic memory cell comprising a free layer, a pinned layer and a tunnel barrier layer disposed on a vertical axis between said free layer and said pinned layer; 
 a lower cell electrode disposed vertically beneath said pinned layer and in electrical contact therewith;    an upper cell electrode disposed vertically over said free layer and in electrical contact therewith;    a set of dielectric sidewalls enclosing said cell electrode and extending substantially vertically along at least an exposed edge of said free layer, said dielectric sidewalls being disposed substantially vertically above an extension of said pinned layer that extends horizontally past said free layer.    
   
   
       12 . A magnetic memory cell according to  claim 11 , in which said dielectric sidewalls are formed from a passivation material, whereby said dielectric sidewalls passivate said exposed edge of said free layer.  
   
   
       13 . A magnetic memory cell according to  claim 11 , in which said dielectric sidewalls extend vertically through a pinning layer that is a sublayer of said pinned layer, whereby said pinning layer has an exposed edge vertically aligned with said exposed edge of said free layer.  
   
   
       14 . A magnetic memory cell according to  claim 13 , in which said dielectric sidewalls are formed from a passivation material, whereby said dielectric sidewalls passivate said exposed edge of said free layer.  
   
   
       15 . A magnetic memory according to  claim 11 , in which said dielectric sidewalls are self-aligned with said extension of said pinned layer, whereby said dielectric sidewalls and said pinned layer have substantially vertical outer edges that are vertically aligned.  
   
   
       16 . A magnetic memory according to  claim 12 , in which said dielectric sidewalls are self-aligned with said extension of said pinned layer, whereby said dielectric sidewalls and said pinned layer have substantially vertical outer edges that are vertically aligned.  
   
   
       17 . A magnetic memory according to  claim 13 , in which said dielectric sidewalls are self-aligned with said extension of said pinned layer, whereby said dielectric sidewalls and said pinned layer have substantially vertical outer edges that are vertically aligned.  
   
   
       18 . A magnetic memory according to  claim 14 , in which said dielectric sidewalls are self-aligned with said extension of said pinned layer, whereby said dielectric sidewalls and said pinned layer have substantially vertical outer edges that are vertically aligned.