Evaporated LaAlO3 films for gate dielectrics

Abstract

A gate dielectric containing LaAlO 3 and method of fabricating a gate dielectric contained LaAlO 3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO 2 . The LaAlO 3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics will have minimal reactions with a silicon substrate or other structures during processing. A LaAlO 3 gate dielectric is formed by evaporating Al 2 O 3 at a given rate, evaporating La 2 O 3 at another rate, and controlling the two rates to provide an amorphous film containing LaAlO 3 on a transistor body region. The evaporation deposition of the LaAlO 3 film is performed using two electron guns to evaporate dry pellets of Al 2 O 3 and La 2 O 3 . The two rates for evaporating the materials are selectively chosen to provide a dielectric film composition having a predetermined dielectric constant ranging from the dielectric constant of an Al 2 O 3 film to the dielectric constant of a La 2 O 3 film. In addition to forming a LaAlO 3 gate dielectric for a transistor, memory devices, and information handling devices such as computers include elements having a LaAlO 3 gate electric with a thin equivalent oxide thickness.

1 . An electronic apparatus comprising: 
 a substrate;    a dielectric layer containing LaAlO 3 , the dielectric layer disposed on the substrate and configured as a part of an electronic device, the dielectric layer including at least Al 2 O 3  or La 2 O 3 .    
     
     
         2 . The electronic apparatus of  claim 1 , wherein the electronic device is a transistor.  
     
     
         3 . The electronic apparatus of  claim 1 , wherein the electronic device is a memory.  
     
     
         4 . The electronic apparatus of  claim 1 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.  
     
     
         5 . The electronic apparatus of  claim 1 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.  
     
     
         6 . A transistor comprising: 
 a first and second source/drain region;    a body region located between the first and second source/drain regions;    a dielectric layer containing LaAlO 3  coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including at least Al 2 O 3  or La 2 O 3 ; and    a gate coupled to the dielectric layer.    
     
     
         7 . The transistor of  claim 6 , wherein the dielectric layer includes Al 2 O 3  and La 2 O 3 .  
     
     
         8 . The transistor of  claim 6 , wherein the dielectric layer is substantially amorphous.  
     
     
         9 . The transistor of  claim 6 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.  
     
     
         10 . The transistor of  claim 6 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.  
     
     
         11 . The transistor of  claim 6 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.  
     
     
         12 . A memory comprising: 
 a number of access transistors, each access transistor including: 
 a first and second source/drain region;  
 a body region located between the first and second source/drain regions;  
 a dielectric layer containing LaAlO 3  coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including Al 2 O 3  or La 2 O 3 ; and  
 a gate coupled to the dielectric layer;  
   a number of wordlines coupled to a number of the gates;    a number of sourcelines coupled to a number of the first source/drain regions; and    a number of bitlines coupled to a number of the second source/drain regions.    
     
     
         13 . The memory of  claim 12 , wherein the dielectric layer includes Al 2 O 3 , and La 2 O 3 .  
     
     
         14 . The memory of  claim 12 , wherein the dielectric layer is substantially amorphous.  
     
     
         15 . The memory of  claim 12 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.  
     
     
         16 . The memory of  claim 12 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.  
     
     
         17 . The memory of  claim 12 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.  
     
     
         18 . An information handling device comprising: 
 a processor;    a memory including: 
 a number of access transistors, each access transistor including: 
 a first and second source/drain region;  
 a body region located between the first and second source/drain regions;  
 a dielectric layer containing LaAlO 3  coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including Al 2 O 3  or La 2 O 3 ; and  
 a gate coupled to the dielectric layer;  
 
 a number of wordlines coupled to a number of the gates;  
 a number of sourcelines coupled to a number of the first source/drain regions;  
 a number of bitlines coupled to a number of the second source/drain regions; and  
   a system bus coupling the processor to the memory.    
     
     
         19 . The information handling device of  claim 18 , wherein the dielectric layer includes Al 2 O 3 , and La 2 O 3 .  
     
     
         20 . The information handling device of  claim 18 , wherein the dielectric layer is substantially amorphous.  
     
     
         21 . The information handling device of  claim 18 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.  
     
     
         22 . The information handling device of  claim 18 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.  
     
     
         23 . The information handling device of  claim 18 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.  
     
     
         24 . A transistor formed by a process comprising: 
 forming a body region coupled between a first source/drain region and a second source/drain region;    evaporating Al 2 O 3  at a first rate;    evaporating La 2 O 3  at a second rate;    controlling the first rate and the second rate to provide a film containing LaAlO 3  on the body region; and    coupling a gate to the film containing LaAlO 3 .    
     
     
         25 . The transistor of  claim 24 , wherein evaporating Al 2 O 3  and evaporating La 2 O 3  includes evaporating dry pellets of Al 2 O 3  and La 2 O 3 .  
     
     
         26 . The transistor of  claim 24 , wherein evaporating Al 2 O 3  and evaporating La 2 O 3  includes evaporating Al 2 O 3  using a first electron gun and evaporating La 2 O 3  using a second electron gun.  
     
     
         27 . The transistor of  claim 24 , wherein controlling the first rate and the second rate includes controlling the first rate and the second rate to selectively provide a film composition having a predetermined dielectric constant.  
     
     
         28 . The transistor of  claim 24 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.  
     
     
         29 . The transistor of  claim 24 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.