Manufacturing method of semiconductor device

Abstract

After deposition of a conductor film made of titanium tungsten over a main surface of a semiconductor substrate formed with grooves, an initial conductor film made of aluminium is further deposited. Subsequently, the conductor film is made to reflow and run into the grooves. Thereafter, while heating, further conductor films are respectively deposited, thereby causing these conductor films to run into the grooves. The provision of the initial conductor film suppresses or prevents aluminium in the further conductor films and silicon in the semiconductor substrate from reacting with each other during reflowing of the conductor films.

1 . A semiconductor device including a plurality of MISFETs, comprising: 
 a semiconductor substrate having a first conductivity type, serving as a drain of the plurality of MISFETs;    a channel-forming region of the plurality of MISFETs, having a second conductivity type opposite to the first conductivity type, formed over the semiconductor substrate;    a plurality of sources of the plurality of MISFETs, having the first conductivity type, formed over the channel-forming region;    a plurality of trenches formed on a main surface of the semiconductor substrate and reaching the semiconductor substrate;    a plurality of gate insulating films of the plurality of MISFETs, formed on an inner wall of the plurality of trenches;    a plurality of gates of the plurality of MISFETs, formed on the plurality of gate insulating films, wherein the plurality of gates are electrically connected;    an interlayer insulating film formed over the plurality of gates;    a source electrode, electrically connected with the plurality of source regions, formed over the interlayer insulating film;    a drain electrode, electrically connected with the semiconductor substrate, formed on a back surface of the semiconductor substrate;    wherein the plurality of gates are electrically connected;    a plurality of contact holes exposing the plurality of the sources and the channel-forming region, formed in the interlayer insulating film; and    a plurality of conductive plugs buried in the plurality of contact holes, wherein the plurality of sources and the source electrode are electrically connected via the plurality of conductive plugs.    
   
   
       2 . A semiconductor device according to  claim 1 , wherein a plurality of grooves under the plurality of contact holes are formed in the main surface of the semiconductor substrate; wherein each of the grooves are formed between the adjacent sources; wherein each of the grooves and contact holes are connected; and wherein the plurality of plugs are buried in the plurality of grooves.  
   
   
       3 . A semiconductor device according to  claim 2 , wherein side surfaces of the sources and the plugs in the grooves are contacted.  
   
   
       4 . A semiconductor device according to  claim 1 , wherein the plurality of plugs are formed by: 
 forming a conductive film in the plurality of contact holes and on a main surface of the interlayer insulating film; and    removing a part of the conductive film, formed on the main surface of the interlayer insulating film, using a CMP method.    
   
   
       5 . A semiconductor device according to  claim 1 , wherein the plurality of MISFETs comprise a power MISFET.  
   
   
       6 . A semiconductor device according to  claim 1 , wherein the semiconductor substrate is comprised of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer; and wherein the second semiconductor layer is formed by an epitaxial growth method.  
   
   
       7 . A semiconductor device according to  claim 1 , wherein the first and second conductivity types are n-type and p-type, respectively.  
   
   
       8 . A semiconductor device according to  claim 1 , wherein an extrinsic gate wiring is formed over the main surface of the semiconductor substrate; wherein the plurality of gates are electrically connected with the extrinsic gate wiring; and wherein the extrinsic gate wiring and the plurality of gates are made of a same layer.  
   
   
       9 . A semiconductor device according to  claim 8 , wherein a gate electrode is formed over the extrinsic gate wiring; wherein the gate electrode and the extrinsic gate wiring are electrically connected; and wherein the gate electrode and the source electrode are made of a same layer.