US2005145850A1PendingUtilityA1

Electrical interconnection and thin film transistor fabrication methods, and integrated circuitry

Priority: May 12, 1993Filed: Feb 22, 2005Published: Jul 7, 2005
Est. expiryMay 12, 2013(expired)· nominal 20-yr term from priority
H10D 30/6734H10D 30/6717H10D 30/6713H10D 30/0314H10D 30/0321Y10S257/903H10B 10/00H10B 10/125
49
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Claims

exact text as granted — not AI-modified
1 - 41 . (canceled)  
   
   
       42 . A semiconductor construction comprising: 
 a first conductive layer over a substrate;    a second conductive layer over the first conductive layer;    a third conductive layer over the second conductive layer; and    a fourth conductive layer in electrical communication with the first and third conductive materials and electrically insulated from the second conductive layer.    
   
   
       43 . The semiconductor construction of  claim 42  wherein the fourth conductive layer is a conductive sidewall spacer.  
   
   
       44 . The semiconductor construction of  claim 42  wherein the first, second, third and fourth conductive layers are comprised by a transistor device.  
   
   
       45 . The semiconductor construction of  claim 42  wherein the third conductive layer overlaps the first conductive layer on a first side and underlaps the first conductive layer on a second side.  
   
   
       46 . The semiconductor construction of  claim 42  wherein the fourth conductive layer comprises conductively doped polysilicon.  
   
   
       47 . The semiconductor construction of  claim 42  wherein the second conductive layer is separated from the fourth conductive layer by an insulative sidewall spacer having a thickness of from about 100 Angstroms to 350 Angstroms. conductive layer is separated from the fourth conductive layer by an insulative sidewall spacer having a thickness of from about  100  Angstroms to  350  Angstroms. S:WI 2228 O 5 MOi .doc  5

Join the waitlist — get patent alerts

Track US2005145850A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.