Non-volatile memory cell with dielectric spacers along sidewalls of a component stack, and method for forming same

Abstract

A disclosed method for forming a non-volatile memory cell includes forming a component stack including an electron trapping layer on a substrate surface. A dielectric layer is formed over the component stack, and a portion is removed such that a remainder of the dielectric layer exists substantially along sidewalls of the component stack. An oxide layer is formed over a bit line in the substrate adjacent to the component stack, and an electrically conductive layer is formed over the component stack and the oxide layer. A described non-volatile memory cell includes a component stack on a substrate surface, the component stack including an electron trapping layer. Multiple dielectric spacers are positioned along sidewalls of the component stack. An oxide layer is positioned over a bit line in the substrate adjacent to the component stack, and an electrically conductive layer is positioned over the component stack and the oxide layer.

1 - 12 . (canceled)  
   
   
       13 . A non-volatile memory cell, comprising: 
 a component stack arranged on a surface of a substrate, wherein the component stack comprises an electron trapping layer;    a plurality of dielectric spacers positioned along and in contact with sidewalls of the component stack;    an oxide layer positioned over and in contact with a bit line existing in the substrate adjacent to the component stack; and    a first electrically conductive layer positioned over and in contact with the component stack and the oxide layer.    
   
   
       14 . The non-volatile memory cell as recited in  claim 13 , wherein the oxide layer is a grown oxide layer.  
   
   
       15 . The non-volatile memory cell as recited in  claim 13 , wherein the dielectric spacers substantially prevent the oxide layer from extending under the component stack during formation of the oxide layer.  
   
   
       16 . The non-volatile memory cell as recited in  claim 13 , wherein the electron trapping layer comprises silicon nitride.  
   
   
       17 . The non-volatile memory cell as recited in  claim 13 , wherein the component stack further comprises a first dielectric layer and a second dielectric layer, and wherein the electron trapping layer is interposed between the first and second dielectric layers.  
   
   
       18 . The non-volatile memory cell as recited in  claim 13 , wherein the component stack further comprises a second electrically conductive layer, and wherein the electron trapping layer is positioned between the second electrically conductive layer and the surface of the substrate.