Semiconductor device including a register to store a value that is representative of device type information

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

1 - 150 . (canceled)  
   
   
       151 . A semiconductor device comprising: 
 an array of memory cells; and    a readable register to store a value that is representative of device type information pertaining to the semiconductor device.    
   
   
       152 . The semiconductor device of  claim 151 , wherein the device type information indicates that the semiconductor device is a memory device.  
   
   
       153 . The semiconductor device of  claim 151 , wherein the device type information indicates how many memory cells are included in the array of memory cells.  
   
   
       154 . The semiconductor device of  claim 151 , wherein the value is output from the semi-conductor device during a control register access.  
   
   
       155 . The semiconductor device of  claim 151 , further comprising: 
 an access time register to store a value that represents a number of clock cycles of an external clock signal to transpire before the semiconductor device outputs data.    
   
   
       156 . The semiconductor device of  claim 151 , further comprising: 
 a plurality of input receivers that includes input receivers to sample operation codes synchronously with respect to an external clock signal;    wherein a first operation code of the operation codes instructs the semiconductor device to store an access time value;    wherein a second operation code of the operation codes instructs the semiconductor device to perform a write operation;    wherein, in response to the second operation code, the semiconductor device samples write data corresponding to the write operation at a time determined using the access time value; and    wherein a third operation code of the operation codes instructs the semiconductor device to access the readable register.    
   
   
       157 . The semiconductor device of  claim 156 , wherein the write data is sampled by the plurality of input receivers, wherein at least a portion of the write data is sampled by the input receivers of the plurality of input receivers that are also used to sample the operation codes.  
   
   
       158 . The semiconductor device of  claim 156 , further comprising: 
 pads coupled to the plurality of input receivers, the pads to interface with signal lines external to the semiconductor device such that the write data is sampled from the pads, wherein, for a pad from which write data is sampled, the semiconductor device samples two bits of write data from the pad during a clock cycle of the external clock signal.    
   
   
       159 . A method of operating a memory controller, the method comprising: 
 providing an operation code that is used to request a value that is representative of device type information pertaining to a memory device; and    receiving the value that is representative of device type information.    
   
   
       160 . The method of  claim 159 , wherein the device type information indicates that the memory device includes memory cells.  
   
   
       161 . The method of  claim 160 , wherein the device type information indicates how many memory cells are included in the memory device.  
   
   
       162 . The method of  claim 159 , further comprising: 
 providing address information that identifies a register that stores the value.    
   
   
       163 . A semiconductor device, comprising: 
 an array of memory cells;    a register to store a value; and    a plurality of input receivers that includes input receivers to sample an operation code synchronously with respect to an external clock signal, wherein the operation code instructs the semiconductor device to output the value stored in the register.    
   
   
       164 . The semiconductor device of  claim 163 , further comprising: 
 pads, coupled to the plurality of input receivers, to interface with signal lines external to the semiconductor device.    
   
   
       165 . The semiconductor device of  claim 164 , wherein the plurality of input receivers sample write data from the pads, wherein, for a pad from which write data is sampled, the semiconductor device samples two bits of the write data from the pad during a clock cycle of the external clock signal.  
   
   
       166 . The semiconductor device of  claim 164 , further comprising: 
 a plurality of output drivers to output data, wherein each output driver of the plurality of output drivers is coupled to a respective pad of the pads.    
   
   
       167 . The semiconductor device of  claim 166 , further comprising: 
 a circuit to receive the external clock signal and to generate an internal clock signal using the external clock signal, wherein the circuit includes feedback to control a timing relationship between the internal clock signal and the external clock signal, wherein the data is output using the internal clock signal.    
   
   
       168 . The semiconductor device of  claim 163 , wherein the value is representative of device type information.  
   
   
       169 . The semiconductor device of  claim 168 , wherein the device type information indicates that the semiconductor device is a memory device.  
   
   
       170 . The semiconductor device of  claim 168 , wherein the device type information indicates how many memory cells are included in the array of memory cells.  
   
   
       171 . A method of operation in a semiconductor device, the method comprising: 
 receiving an operation code synchronously with respect to an external clock signal; and    outputting, in response to the operation code, a value that is representative of device type information pertaining to the semiconductor device.    
   
   
       172 . The method of  claim 171 , wherein the device type information indicates that the semiconductor device includes an array of memory cells.  
   
   
       173 . The method of  claim 172 , wherein the device type information indicates how many memory cells are included in the array of memory cells.  
   
   
       174 . The method of  claim 171 , further comprising: 
 receiving address information that identifies a register that stores the value.    
   
   
       175 . The method of  claim 174 , wherein the device type information indicates that the semiconductor device includes an array of memory cells.  
   
   
       176 . The method of  claim 175 , wherein the device type information indicates how many memory cells are included in the array of memory cells.  
   
   
       177 . The method of  claim 174 , further comprising: 
 receiving the value; and    storing the value in the register.    
   
   
       178 . The method of  claim 177 , further comprising: 
 receiving an operation code that instructs the semiconductor device to sample the value, wherein receiving the value includes sampling the value synchronously with respect to the external clock signal in response to the operation code that instructs the semiconductor device to sample the value.    
   
   
       179 . A semiconductor device comprising: 
 an array memory cells;    a readable register to store a value that is representative of device type information pertaining to the semiconductor device;    an access time register to store a value that represents a number of clock cycles of an external clock signal to transpire before the semiconductor device outputs data;    a circuit to receive the external clock signal, the circuit to generate an internal clock signal using the external clock signal, wherein the circuit includes feedback to control a timing relationship between the internal clock signal and the external clock signal; and    an output driver to output two bits of the data during a clock cycle of the external clock signal, wherein the data is output using the internal clock signal.    
   
   
       180 . The semiconductor device of  claim 179 , wherein the device type information indicates how many memory cells are included in the array of memory cells.  
   
   
       181 . The semiconductor device of  claim 179 , wherein the value is output from the semiconductor device during a control register access.  
   
   
       182 . The semiconductor device of  claim 181 , further comprising: 
 a plurality of input receivers that includes input receivers to sample operation codes synchronously with respect to the external clock signal;    wherein a first operation code of the operation codes instructs the semiconductor device to store the value that represents the number of clock cycles to transpire before the semiconductor device outputs data;    wherein a second operation code of the operation codes instructs the semiconductor device to perform a write operation;    wherein, in response to the second operation code, the semiconductor device samples write data corresponding to the write operation, the semiconductor device sampling the write data at a time determined using the value that represents the number of clock cycles to transpire before the semiconductor device outputs data; and    wherein a third operation code of the operation codes instructs the semiconductor device to initiate the control register access.    
   
   
       183 . The semiconductor device of  claim 182 , wherein the write data is sampled by the plurality of input receivers, wherein at least a portion of the write data is sampled by the input receivers of the plurality of input receivers that are also used to sample the operation codes.  
   
   
       184 . A semiconductor memory device comprising: 
 an array of memory cells; and    means for storing a value that is representative of device type information that pertains to the semiconductor device.