Circuit for modifying a clock signal to achieve a predetermined duty cycle

Abstract

The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator ( 102 ) configured in a feedback loop, the output of the charge pump integrator ( 102 ) operable as a controlling node to delay inverter ( 115 ). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator ( 102 ) will, through PBIAS, cause delay inverter 115 to delay of the rising edge of CLKIN through delay inverter ( 115 ). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.

1 - 17 . (canceled)  
   
   
       18 . A circuit adapted to modify a clock signal, the circuit comprising: 
 a first current source and a second current source outputting a charge with different polarities;    an output node coupling the first and second current sources together;    a capacitor for storing charge;    a delay inverter being coupled to the output node of the current sources and the capacitor;    the delay inverter comprising a plurality of transistors inverting and switching charge through the delay inverter;    the first and second current sources and capacitor operable to output charge through the delay inverter at a predetermined ratio; and    the circuit operable to output a clock signal with the predetermined duty cycle using low power.    
   
   
       19 . The circuit of  claim 18 , wherein the circuit power consumption is between 2 and 3 micro-amps.  
   
   
       20 . The circuit of  claim 18 , wherein the circuit is operable to accept a clock signal with a duty cycle greater than 50% and output the clock signal with the predetermined duty cycle of approximately 50%.  
   
   
       21 . The circuit of  claim 18 , further comprising a delay circuit in series with the delay inverter operable to apply a fixed delay to a falling edge of the signal.  
   
   
       22 . The circuit of  claim 21 , wherein the circuit is operable to accept a clock signal with a duty cycle lesser than or greater than 50% and output the clock signal with the predetermined duty cycle.  
   
   
       23 . The circuit of  claim 21 , wherein the delay circuit includes a weak N channel transistor with a fixed bias operable to apply a fixed amount of delay on the falling edge of the signal.  
   
   
       24 . A delay inverter circuit for manipulating a signal operable to output the signal with a predetermined duty cycle, the circuit comprising: 
 a first transistor having an input, output and control;    a second transistor having an input, output and control;    the first transistor and the second transistor having the same polarity types;    a third transistor with an input, output and control;    the third transistor having a polarity type opposite that of the first and second transistors;    a first voltage rail;    the input of the first transistor being coupled to the first voltage rail;    the control of the first transistor being current controlled;    the output of the first transistor being coupled to the input of the second transistor;    the output of the second transistor being coupled to the output of the third transistor;    a second voltage rail;    the input of the third transistor being coupled to the second voltage rail; and    the control of the second transistor being coupled to the control of the third transistor.    
   
   
       25 . The delay inverter circuit of  claim 24 , further comprising: 
 an input node being coupled to the control of the second transistor which is coupled to the control of the third transistor; and    an output node being coupled to the output of the second transistor which is coupled to the output of the third transistor.    
   
   
       26 . The delay inverter circuit of  claim 24 , further comprising a charge pump integrator operable to control the first transistor.  
   
   
       27 . The delay inverter circuit of  claim 24 , whereby the transistors comprise MOS transistors.  
   
   
       28 . The delay inverter circuit of  claim 27 , wherein the first and second transistors comprise PMOS transistors and the third transistor comprises an NMOS transistor.  
   
   
       29 . The delay inverter circuit of  claim 28 , further comprising the first voltage rail being designated Vdd and the second voltage rail being designated Vss.  
   
   
       30 . The delay inverter circuit of  claim 27 , wherein the first and second transistors comprise NMOS transistors and the third transistor comprises an PMOS transistor.  
   
   
       31 . The delay inverter circuit of  claim 30 , further comprising the first voltage rail being designated Vss and the second voltage rail being designated Vdd.  
   
   
       32 . The delay inverter circuit of  claim 24 , wherein the circuit is operable to accept a clock signal with a duty cycle greater than 50% and output the clock signal with the predetermined duty cycle of approximately 50%.  
   
   
       33 . The delay inverter circuit of  claim 24 , further comprising a delay circuit in series with the delay inverter circuit operable to apply a fixed delay to a falling edge of the signal.  
   
   
       34 . The delay inverter circuit of  claim 33 , wherein the circuit is operable to accept a clock signal with a duty cycle lesser than or greater than 50% and output the clock signal with the predetermined duty cycle.  
   
   
       35 . The circuit of  claim 33 , wherein the delay circuit includes a weak N channel transistor with a fixed bias operable to apply a fixed amount of delay on the falling edge of the signal.  
   
   
       36 . A delay inverter circuit for manipulating a signal operable to output the signal with a predetermined duty cycle, the circuit comprising: 
 a first transistor having an input, output and control;    a second transistor having an input, output and control;    the first transistor and the second transistor having the same polarity types;    a third transistor with an input, output and control;    the third transistor having a polarity type opposite that of the first and second transistors;    a first voltage rail;    the input of the first transistor being coupled to the first voltage rail;    the output of the first transistor being coupled to the input of the second transistor;    the output of the second transistor being coupled to the output of the third transistor;    the control of the second transistor being current controlled;    a second voltage rail;    the input of the third transistor being coupled to the second voltage rail; and    the control of the first transistor being coupled to the control of the third transistor.    
   
   
       37 . The delay inverter circuit of  claim 36 , further comprising: 
 an input node being coupled to the control of the first transistor which is coupled to the control of the third transistor; and    an output node being coupled to the output of the second transistor which is coupled to the output of the third transistor.    
   
   
       38 . The delay inverter circuit of  claim 36 , further comprising a charge pump integrator operable to control the second transistor.  
   
   
       39 . The delay inverter circuit of  claim 36 , whereby the transistors comprise MOS transistors.  
   
   
       40 . The delay inverter circuit of  claim 39 , wherein the first and second transistors comprise PMOS transistors and the third transistor comprises an NMOS transistor.  
   
   
       41 . The delay inverter circuit of  claim 40 , further comprising the first voltage rail being designated Vdd and the second voltage rail being designated Vss.  
   
   
       42 . The delay inverter circuit of  claim 39 , wherein the first and second transistors comprise NMOS transistors and the third transistor comprises a PMOS transistor.  
   
   
       43 . The delay inverter circuit of  claim 42 , further comprising the first voltage rail being designated Vdd and the second voltage rail being designated Vss.  
   
   
       44 . The delay inverter circuit of  claim 36 , wherein the circuit is operable to accept a clock signal with a duty cycle greater than 50% and output the clock signal with the predetermined duty cycle of approximately 50%.  
   
   
       45 . The delay inverter circuit of  claim 36 , further comprising a delay circuit in series with the delay inverter circuit operable to apply a fixed delay to a falling edge of the signal.  
   
   
       46 . The delay inverter circuit of  claim 45 , wherein the circuit is operable to accept a clock signal with a duty cycle lesser than or greater than 50% and output the clock signal with the predetermined duty cycle.  
   
   
       47 . The circuit of  claim 45 , wherein the delay circuit includes a weak N channel transistor with a fixed bias operable to apply a fixed amount of delay on the falling edge of the signal.