Fabrication methods for electronic system modules

Abstract

This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described.

1 . An electronic module comprising: 
 a flexible interconnection circuit having conductive traces with a width of five microns or less and a trace pitch of ten microns or less, and,    a plurality of integrated circuit chips mounted on said interconnection circuit using flip chip bonding.    
   
   
       2 . The electronic module of  claim 1  wherein said flip chip bonds include stud bumps on each input/output pad of said integrated circuit chips, and corresponding wells filled with solder on said interconnection circuit, said wells connecting with traces connected to nodes of said interconnection circuit.  
   
   
       3 . The electronic module of  claim 2  wherein said nodes of said interconnection circuit connect with module access pads provided at the surface of said electronic module.  
   
   
       4 . The electronic module of  claim 3  wherein said module access pads connect with wells filled with solder.  
   
   
       5 . The electronic module of claims  2  or  4  wherein said wells filled with solder are spaced with a pitch of 100 microns or less.  
   
   
       6 . The electronic module of  claim 1  wherein said integrated circuit chips are thermally coupled to a heat sink.  
   
   
       7 . The electronic module of  claim 6  wherein said thermal coupling includes a layer of conductive adhesive between faces of said integrated circuits or between films covering said faces of said integrated circuits and a surface of said heat sink.  
   
   
       8 . The electronic module of  claim 6  wherein said heat sink includes a cooling fluid.  
   
   
       9 . A method for fabricating a multi-layer interconnection circuit comprising the steps of: 
 providing a rigid carrier,    applying a base polymer layer on said rigid carrier,    fabricating a multi-layer interconnection circuit having alternate layers of patterned metal and patterned polymer on said base layer, said patterned metal layers having traces with line widths of 5 microns or less and a metal trace pitch of 10 microns or less.    
   
   
       10 . A method for fabricating a multi-layer interconnection circuit comprising the steps of: 
 providing a rigid carrier,    applying a release layer to said rigid carrier,    applying a base polymer layer on said release layer,    fabricating a multi-layer interconnection circuit having alternate layers of patterned metal and patterned polymer on said base polymer layer, said patterned metal layers having traces with line widths of 5 microns or less and a metal trace pitch of 10 microns or less.    
   
   
       11 . A method for fabricating an interconnection device comprising the steps of: 
 providing a rigid carrier,    applying a release layer to said rigid carrier,    applying a base polymer layer on said release layer,    fabricating a multi-layer interconnection circuit having alternate layers of patterned metal and patterned polymer on said base polymer layer, said patterned metal layers having traces with line widths of 5 microns or less and a metal trace pitch of 10 microns or less,    applying a polymer layer over said interconnection circuit, said polymer layer having openings positioned over selected traces, and,    filling said openings with solder.    
   
   
       12 . The method of claims  9 ,  10  or  11  wherein said rigid carrier is a glass carrier.  
   
   
       13 . The method of claims  9 ,  10  or  11  wherein said patterned polymer is photo-defined.  
   
   
       14 . The method of claims  9 ,  10  or  11  wherein said interconnection circuit or said interconnection device is separated from said rigid carrier after processing.  
   
   
       15 . The method of claims  9 ,  10  or  11  wherein said interconnection circuit is flexible.  
   
   
       16 . The method of claims  10  or  11  wherein said release layer is a fluorinated silicone.  
   
   
       17 . The method of  claim 10  or  11  wherein said release layer is not present near the edges of said rigid carrier, to provide an edge region of strong adhesion between said base polymer layer and said rigid carrier.  
   
   
       18 . The method of  claim 10  or  11  wherein said release layer is not present in streets provided at the periphery of each of said multi-layer interconnection circuits, said streets providing regions of strong adhesion between said base polymer layer and said rigid carrier.  
   
   
       19 . The method of  claim 12  wherein said glass carrier measures more than 500 mm on a side.  
   
   
       20 . An interconnection device comprising: 
 a rigid substrate,    one or more layers of patterned metal having traces with line widths of 20 microns or less and a metal trace pitch of 40 microns or less,    a polymer layer applied over said traces having openings positioned over selected traces, and,    solder filling each of said openings.    
   
   
       21 . A stacked contact formed between a plurality of patterned metal layers of an interconnection circuit, comprising: 
 planarizing layers of patterned polymer between each of said patterned metal layers,    contact windows with tapered walls in each of said planarizing layers, wherein said contact windows are positioned above contacting traces of metal on a preceding layer, and,    patterned metal of succeeding metal layers with traces positioned over said contact windows to contact said contacting traces of metal on said preceding layers.    
   
   
       22 . The stacked contact of  claim 21  wherein said patterned polymer is photo-defined.  
   
   
       23 . The stacked contact of  claim 21  wherein said patterned polymer is photo-imageable Cyclotene.  
   
   
       24 . The stacked contact of  claim 21  wherein trace stubs are provided at each metal layer in the stacked contact.  
   
   
       25 . A multi-layer interconnection circuit wherein a stacked contact providing connection between all of the conducting layers is included at each input/output pad of each integrated circuit chip to be assembled on said multi-layer interconnection circuit.  
   
   
       26 . The multi-layer interconnection circuit of  claim 25  wherein contacts of said multi-layer interconnection circuit, other than said stacked contacts, are limited to two-level contacts where a desired minimum trace pitch is to be maintained.  
   
   
       27 . A method for forming closely spaced wells filled with solder on a flexible interconnection circuit comprising the steps of: 
 providing a rigid carrier for said interconnection circuit,    applying a layer of polymer on said interconnection circuit,    etching openings in said polymer layer at each input/output pad, and,    depositing solder paste in said openings.    
   
   
       28 . The method of  claim 27  wherein said solder paste is deposited in said openings using a squeegee.  
   
   
       29 . A method for assembling integrated circuit chips on an interconnection circuit having conductive traces comprising the steps of: 
 providing a stud bump on each input/output pad of each of said integrated circuit chips,    fabricating wells filled with solder on said interconnection circuit, said wells having a one-to-one correspondence with said input/output pads of said integrated circuit chips and said wells are positioned above selected conductive traces,    inserting said stud bumps of each of said integrated circuit chips in said corresponding wells filled with solder, and,    heating and cooling said solder to make permanent connections.    
   
   
       30 . The method of  claim 29  wherein said interconnection circuit is flexible.  
   
   
       31 . A circuit assembly comprising: 
 a plurality of integrated circuits having stud bumps at each input/output pad,    an interconnection circuit having wells filled with solder, said wells corresponding in a one-to-one relationship with said stud bumps of said integrated circuits, and,    electrical and mechanical bonding at each of said input/output pads wherein each of said stud bumps connects with solder in each of said wells to form a permanent connection.    
   
   
       32 . The circuit assembly of  claim 30  wherein said interconnection circuit is flexible.  
   
   
       33 . A method for building a tested circuit assembly having multiple integrated circuit chips on an interconnection circuit, comprising the steps of: 
 stud bumping each input/output pad of each of said integrated circuit chips,    fabricating wells filled with solder on said interconnection circuit, said wells having a one-to-one correspondence with said input/output pads of said integrated circuit chips and each well is connected to a trace of said interconnection circuit chip,    selecting the first integrated circuit chip to be assembled,    inserting stud bumps of said integrated circuit chip in corresponding wells of said interconnection circuit,    heating and cooling said solder to make a permanent connection between said stud bumps of said integrated circuit chip and said corresponding wells,    testing said integrated circuit chip in said circuit assembly,    if the result of said testing of said integrated circuit chip is “pass”, selecting the next integrated circuit chip to be assembled and continuing at step d until all of said integrated circuit chips have been assembled and have tested with a result of “pass”,    if the result of said test of said integrated circuit chip is “fail”, applying heat until said solder melts in said corresponding wells of said failed integrated circuit chip, and removing said stud bumps of said failed integrated circuit from said corresponding wells,    inspecting said corresponding wells and touching up if necessary,    selecting a replacement for said failed integrated circuit and continuing at step d. until all of said integrated circuit chips have been assembled and have tested with a result of “pass”.    
   
   
       34 . The method of  claim 33  wherein said circuit assembly includes a module access port for connecting to a tester, said module access port comprising an array of module access pads, each of said module access pads connecting to a node of said interconnection circuit.  
   
   
       35 . A method for testing an interconnection circuit comprising the steps of: 
 providing a module access port including an array of module access pads, each module access pad connecting to a node of said interconnection circuit,    providing means to connect from said module access port to a tester, thereby connecting nodes of said interconnection circuit to corresponding nodes of said tester, and,    testing said nodes of said interconnection circuit for correct connectivity.    
   
   
       36 . A method for incremental assembly and test of a circuit assembly comprising the sequential steps of: 
 providing a tested interconnection circuit,    providing a full set of electronic components required by said circuit assembly,    selecting the first electronic component to be assembled,    assembling said electronic component on said interconnection circuit,    testing said electronic component in the system environment including the subset of electronic components already assembled,    if said electronic component operates correctly in said system environment, selecting the next electronic component to be assembled,    if said electronic component is a defective component in said system environment, removing said defective component and selecting a replacement electronic component, and,    repeating steps d through g until all of said electronic components are assembled and tested on said interconnection circuit with none of said defective components remaining, to create a version of said circuit assembly meeting all of the tested specifications.    
   
   
       37 . The method of  claim 36  wherein the unit of assembly is a group of components rather than a single component.  
   
   
       38 . The method of  claim 36  wherein said testing of said electronic components is performed using special-purpose electronic components that are the first of said electronic components to be assembled on said circuit assembly.  
   
   
       39 . The method of  claim 36  wherein said testing of said electronic components is performed using an external tester.  
   
   
       40 . A test fixture for testing an electronic assembly comprising: 
 a rigid substrate,    an interconnection circuit fabricated on said rigid substrate having two sets of input/output pads, one set connecting to said circuit assembly and another set connecting with a tester, said interconnection circuit having conductive traces that connect between corresponding input/output pads of each of said sets, and,    a stud bump at each of said input/output pads in each of said sets.    
   
   
       41 . The test fixture of  claim 40  and including a fine pitch of said input/output pads at the end connecting with said circuit assembly and a coarser pitch of said input/output pads at the end connecting with said tester.  
   
   
       42 . The test fixture of  claim 40  and including three or more sets of input/output pads for connection to three or more circuit assemblies or electronic systems.  
   
   
       43 . A module cable for connecting between a parent module and another electronic system comprising: 
 a rigid carrier for supporting said module cable during manufacture and assembly, including the steps of connecting said module cable to said parent module and to said electronic system,    a base polymer layer on said rigid carrier,    an interconnection circuit fabricated on said base polymer layer having two sets of input/output pads, one set at the parent end of said module cable and one set at the other end, with conductive traces that connect in a one-to-one relationship between each of said input/output pads in each of said sets, and,    a stud bump at each input/output pad in each of said sets of input/output pads of said module cable.    
   
   
       44 . The module cable of  claim 43  and including a release layer between said rigid carrier and said base polymer layer.  
   
   
       45 . The module cable of  claim 43  and including three or more sets of I/O pads for connection to three or more electronic modules or systems.  
   
   
       46 . The module cable of  claim 43  wherein said rigid carrier is separated from said module cable after said connecting steps are performed.  
   
   
       47 . The module cable of  claim 43  wherein a portion of said rigid carrier is removed after each of said connecting steps is performed.  
   
   
       48 . A method for building an electronic module with an attached module cable comprising the steps of: 
 providing a module cable having a rigid carrier, a base polymer layer, an interconnection circuit fabricated on said base polymer layer having two sets of input/output pads, a first set at a first end of said module cable and a second set at the other end, with conductive traces that connect in a one-to-one relationship between one of said input/output pads in said first set and a corresponding input/output pad in said second set, and a stud bump at every input/output pad in each of said first and second sets of input/output pads of said module cable,    providing wells filled with solder at a surface of said electronic module, said wells connecting with nodes of said electronic module and having a one-to-one relation with said first set of input/output pads of said module cable,    inserting said stud bumps of said first set of input/output pads in said wells,    applying heat until said solder melts, and,    cooling to form a permanent connection between said module cable and said electronic module.    
   
   
       49 . The method of  claim 48  and including the step of removing a portion of said rigid carrier after said permanent connection has been made.  
   
   
       50 . The method of  claim 48  and including the step of removing said rigid carrier after a permanent connection has been made to an electronic system at each end of said module cable.  
   
   
       51 . The method of  claim 48  and including 3 or more sets of input/output pads on said module cable, each set connecting with a separate electronic module or system.  
   
   
       52 . The method of  claim 51  and including the step of removing said rigid carrier after said permanent connections have been made to said separate electronic modules or systems.  
   
   
       53 . A hermetically sealed electronic circuit module having attached components comprising: 
 a module access port including an array of module access pads,    a dielectric layer coating said circuit module at surfaces having attached components, with openings at said module access pads, and,    a continuous metal film coating the entire surface of said circuit module, except for openings at said module access pads.    
   
   
       54 . An electro-magnetically shielded electronic circuit module having attached components comprising: 
 a module access port including an array of module access pads,    a dielectric layer coating said circuit module at surfaces having attached components, with openings at said module access pads, and,    a continuous metal film coating the entire surface of said circuit module, except for openings at said module access pads.    
   
   
       55 . The electro-magnetically shielded circuit module of  claim 54  wherein said continuous metal film is grounded.