Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates

Abstract

A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

1 . A wafer assembly comprising: 
 a lower wafer comprising a plurality of mirror devices;    an upper wafer bonded in spaced apart relationship to the lower wafer; one or more intermediate wafers bonded between the upper and lower wafer and having open areas corresponding to each mirror device location.    
     
     
         2 . The wafer assembly of  claim 1 , further comprising a light blocking material on the upper wafer.  
     
     
         3 . The wafer assembly of  claim 2 , wherein the light blocking material is provided as a rectangular mask at each mirror array device location.  
     
     
         4 . The wafer assembly of  claim 1 , wherein each mirror device comprises a plurality of mirror elements.  
     
     
         5 . The wafer assembly of  claim 1 , wherein a cavity is defined by the lower wafer, the one or more intermediate wafers and the upper wafer, and wherein the mirror devices comprise mirror elements that can move within the cavity.  
     
     
         6 . The wafer assembly of  claim 5 , wherein the lower wafer is a semiconductor wafer.  
     
     
         7 . The wafer assembly of  claim 6 , wherein the lower wafer is a silicon wafer.  
     
     
         8 . The wafer assembly of  claim 1 , wherein the upper wafer is a light transmissive wafer.  
     
     
         9 . The wafer assembly of  claim 6 , wherein the upper wafer is a glass or quartz wafer.  
     
     
         10 . The wafer assembly of  claim 1 , wherein the upper and lower wafer are cut or scribed around each mirror device.  
     
     
         11 . The wafer assembly of  claim 1 , wherein the upper and lower wafers are round or substantially round.  
     
     
         12 . The wafer assembly of  claim 11 , wherein the lower wafer is  12  inches in diameter.  
     
     
         13 . The wafer assembly of  claim 9 , wherein the mirror elements are substantially square micromirrors.  
     
     
         14 . The wafer assembly of  claim 9 , further comprising torsion hinges that allow the mirror elements to move relative to the upper and lower wafers.  
     
     
         15 . The wafer assembly of  claim 14 , wherein the hinges have a thickness of 50 Å to 2100 Å.  
     
     
         16 . The wafer assembly of  claim 9 , wherein the hinges are formed in the same plane as the mirror element.  
     
     
         17 . The wafer assembly of  claim 9 , wherein the hinges are formed separated from and parallel to the mirror element in a different plane.  
     
     
         18 . The wafer assembly of  claim 14 , wherein the lower wafer comprises an array of electrodes disposed to electrostatically deflect the mirror elements.  
     
     
         19 . The wafer assembly of  claim 18 , wherein the electrodes are designed to run at 0-5 V.  
     
     
         20 . The wafer assembly of  claim 9 , comprising an SRAM cell at each mirror element.  
     
     
         21 . The wafer assembly of  claim 1 , wherein a mirror device of the plurality of mirror devices has XGA resolution.  
     
     
         22 . The wafer assembly of  claim 1 , wherein the wafers are bonded together with an adhesive.  
     
     
         23 . The wafer assembly of  claim 9 , wherein the wafers are bonded together with an epoxy.  
     
     
         24 . The wafer assembly of  claim 9 , wherein the mirror devices comprise a stiction treatment.  
     
     
         25 . The wafer assembly of  claim 1 , wherein wafers are anodically bonded together.  
     
     
         26 . The wafer assembly of  claim 17 , wherein the wafers are solder bonded together.  
     
     
         27 . The wafer assembly of  claim 1 , wherein the wafers are compression, anodic, fusion or metal eutectic bonded together.  
     
     
         28 . The wafer assembly of  claim 1 , wherein the mirror devices have an anti-stiction layer.  
     
     
         29 . The wafer assembly of  claim 20 , wherein the gap between the upper and lower wafer is from 1 to 10 um.  
     
     
         30 . The wafer assembly of  claim 22 , wherein the adhesive is a UV cured adhesive.  
     
     
         31 . The wafer assembly of  claim 23 , wherein the epoxy is a UV cured epoxy.  
     
     
         32 . The wafer assembly of  claim 1 , comprising saw streets on the lower wafer.  
     
     
         33 . The wafer assembly of  claim 32 , wherein the saw streets are to a depth of 50 to 90% of the wafer thickness.  
     
     
         34 . The wafer assembly of  claim 9 , wherein the upper wafer and lower wafer comprise saw streets from 50 to 95% of the wafer thickness.  
     
     
         35 . The wafer assembly of  claim 23 , wherein the mirror devices comprise at least 1000 movable mirrors.  
     
     
         36 . The wafer assembly of  claim 20 , wherein the mirror devices comprise between 1 and 6 million movable elements.  
     
     
         37 . The wafer assembly of  claim 20 , wherein the mirror devices comprises a plurality of micromirrors disposed within a rectangular array.  
     
     
         38 . The wafer assembly of  claim 1 , comprising horizontal and vertical score or partial saw lines.  
     
     
         39 . The wafer assembly of  claim 38 , wherein the score or partial saw lines are offset from each other at least in one of the horizontal or vertical directions.  
     
     
         40 . The wafer assembly of  claim 1 , wherein the mirror devices on the lower wafer comprise circuitry and micromechanical structures formed monolithically on the same substrate.  
     
     
         41 . The wafer assembly of  claim 40 , further comprising areas of lubricant.  
     
     
         42 . The wafer assembly of  claim 5 , wherein a plurality of cavities are formed and defined by each open portion of the one or more intermediate wafers and the upper and lower wafers with a mirror device comprising a plurality of movable mirrors are disposed in each cavity.  
     
     
         43 . The wafer assembly of  claim 42 , further comprising getter material in each cavity.  
     
     
         44 . The wafer assembly of  claim 43 , further comprising lubricant in each cavity.  
     
     
         45 . The wafer assembly of  claim 44 , wherein the lubricant is an organic lubricant.  
     
     
         46 . The wafer assembly of  claim 1 , wherein one or more of a mask, lubricant or getter is present on the upper wafer.  
     
     
         47 . The wafer assembly of  claim 1 , wherein the lower wafer is held on a lower packaging substrate.  
     
     
         48 . The wafer assembly of  claim 47 , wherein a distance between the upper and lower wafer is from 1 to 100 microns.  
     
     
         49 . The wafer assembly of  claim 48 , wherein a distance between the upper and lower wafer is from 1 to 20 microns.  
     
     
         50 . The wafer assembly of  claim 43 , wherein the getter is a moisture getter.  
     
     
         51 . The wafer assembly of  claim 43 , wherein the getter is a particle getter.  
     
     
         52 . The wafer assembly of  claim 43 , wherein the getter is a hydrogen getter.  
     
     
         53 . The wafer assembly of  claim 43 , wherein the getter is a metal oxide or zeolite getter.  
     
     
         54 . The wafer assembly of  claim 43 , wherein the getter is a combination getter.  
     
     
         55 . A substrate assembly comprising: 
 a lower semiconductor substrate comprising a plurality of MEMS devices;    an upper light transmissive substrate bonded in spaced apart relationship to the lower substrate; and    one or more intermediate substrates bonded between the upper and lower substrates and with open areas defining cavities at each MEMS device location.    
     
     
         56 . The substrate assembly of  claim 55 , further comprising a light blocking material on the light transmissive substrate.  
     
     
         57 . The substrate assembly of  claim 55 , wherein each MEMS device comprises a plurality of micromirrors.  
     
     
         58 . The substrate assembly of  claim 56 , wherein the light blocking material is provided as a rectangular mask at each MEMS device location.  
     
     
         59 . The substrate assembly of  claim 55 , wherein the upper and lower substrates have score or partial saw lines in horizontal and vertical directions.  
     
     
         60 . The substrate assembly of  claim 55 , wherein the score or partial saw lines are from 50 to 95% of the thickness of the substrate.  
     
     
         61 . The substrate assembly of  claim 57 , wherein the micromirrors comprises mirror elements and hinges that are formed separated from and parallel to the mirror element in a different plane.  
     
     
         62 . The substrate assembly of  claim 55 , wherein the substrates are bonded together with an adhesive.  
     
     
         63 . The substrate assembly of  claim 62 , wherein the adhesive is an epoxy.  
     
     
         64 . The substrate assembly of  claim 59 , wherein the score or partial saw lines on the upper and lower substrates are offset from each other.  
     
     
         65 . The substrate assembly of  claim 55 , wherein the MEMS devices comprise a getter within the cavity at each MEMS device location.  
     
     
         66 . The substrate assembly of  claim 65 , wherein the MEMS devices comprise a lubricant within the cavity at each MEMS device location.  
     
     
         67 . The substrate assembly of  claim 55 , wherein the lower substrate is held on a lower packaging substrate.  
     
     
         68 . The substrate assembly of  claim 67 , wherein a distance between the upper and lower substrates is from 1 to 100 microns.  
     
     
         69 . The substrate assembly of  claim 65 , wherein the getter is a moisture, particle or hydrogen getter.