Capacitor for semiconductor device and fabricating method thereof

Abstract

A capacitor for a semiconductor device includes a first inter metal dielectric layer is disposed on a substrate. A first electrode is disposed on the first inter metal dielectric layer. A second electrode partially overlaps the first electrode. A first dielectric layer is disposed between the first and second electrodes. A third electrode partially overlaps the second electrode. A second dielectric layer is disposed between the second and third electrodes. An etch stop layer is disposed on the first, second, and third electrodes. A second inter metal dielectric layer is formed on the etch stop layer and includes first, second, and third via holes exposing the first and third electrodes and the etch stop layer. First, second, and third plugs are disposed in the first, second, and third via holes.

1 . A capacitor for a semiconductor device, comprising: 
 a first inter metal dielectric layer disposed on a substrate;    a first electrode disposed on the first inter metal dielectric layer;    a second electrode partially overlapping the first electrode;    a first dielectric layer disposed between the first and second electrodes;    a third electrode partially overlapping the second electrode;    a second dielectric layer disposed between the second and third electrodes;    an etch stop layer disposed on the first, second, and third electrodes;    a second inter metal dielectric layer formed on the etch stop layer and comprising first, second, and third via holes exposing the first and third electrodes and the etch stop layer; and    first, second, and third plugs disposed in the first, second, and third via holes.    
   
   
       2 . The capacitor according to  claim 1 , wherein the etch stop layer comprises a nitride material.  
   
   
       3 . The capacitor according to  claim 1 , wherein at least one of the inter metal dielectric layers comprises an oxide material.  
   
   
       4 . The capacitor according to  claim 1 , wherein a portion of the first dielectric layer disposed between the first and second electrodes has a thickness less than an adjacent portion of the first dielectric layer, and a portion of the second dielectric layer disposed between the second and third parts has a thickness less than an adjacent portion of the second dielectric layer.  
   
   
       5 . The capacitor according to  claim 1 , wherein the first electrode, the first dielectric layer, the second electrode, the second dielectric layer, and the third electrode are sequentially layered.  
   
   
       6 . The capacitor according to  claim 5 , wherein the first via hole exposes the second electrode at a position that does not overlap the first and third electrodes, the second via hole exposes the third electrode, and the third via hole exposes the first electrode at a position that does not overlap the second and third electrodes.  
   
   
       7 . A method for fabricating a capacitor for a semiconductor device, comprising: 
 forming a first inter metal dielectric layer on a substrate;    forming a first metal layer to fill a trench on the first inter metal dielectric layer;    polishing the first metal layer using a chemical mechanical polishing to form a first electrode;    forming a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer on the first electrode;    patterning the third metal layer using a selective etching to form a third electrode;    patterning the second metal layer using the selective etching to form a second electrode that overlaps the first electrode and the third electrode;    forming an etch stop layer and a second inter metal dielectric layer to cover the first, second, and third electrodes;    etching the second inter metal dielectric layer using a selective photolithography process to form via holes to expose the etch stop layer;    removing the etch stop layer to expose the first, second, and third electrodes;    filling the via holes to form plugs, the plugs electric connecting with the first, second, and third electrodes; and    forming metal wirings on the second inter metal dielectric layer to conduct electricity to the first to third electrodes through the plugs.    
   
   
       8 . The method according to  claim 7 , wherein the etch stop layer comprises a nitride material.  
   
   
       9 . The method according to  claim 7 , wherein the inter metal dielectric layer comprises an oxide material.  
   
   
       10 . A capacitor for a semiconductor device, comprising: 
 a first dielectric layer disposed on a substrate;    a first electrode disposed on the first dielectric layer;    a second electrode partially overlapping the first electrode;    a second dielectric layer disposed between the first and second electrodes;    a third electrode partially overlapping the second electrode;    a third dielectric layer disposed between the second and third electrodes;    an etch stop layer disposed on the first, second, and third electrodes;    a fourth dielectric layer formed on the etch stop layer and comprising first, second, and third via holes exposing the first and third electrodes and the etch stop layer; and    first, second, and third plugs disposed in the first, second, and third via holes.    
   
   
       11 . The capacitor according to  claim 10 , wherein the etch stop layer comprises a nitride material.  
   
   
       12 . The capacitor according to  claim 10 , wherein at least one of the dielectric layer comprises an oxide material.  
   
   
       13 . The capacitor according to  claim 10 , wherein at least one of the first and fourth dielectric layers comprises an oxide material.  
   
   
       14 . The capacitor according to  claim 10 , wherein a portion of the second dielectric layer disposed between the first and second electrodes has a thickness less than an adjacent portion of the second dielectric layer, and a portion of the third dielectric layer disposed between the second and third parts has a thickness less than an adjacent portion of the third dielectric layer.  
   
   
       15 . The capacitor according to  claim 17 , wherein the first via hole exposes the second electrode at a position that does not overlap the first and third electrodes, the second via hole exposes the third electrode, and the third via hole exposes the first electrode at a position that does not overlap the second and third electrodes.  
   
   
       16 . The capacitor according to  claim 17 , wherein at least one of the first and fourth dielectric layers comprises an inter metal dielectric layer.  
   
   
       17 . The capacitor according to  claim 10 , wherein the first electrode, the second dielectric layer, the second electrode, the third dielectric layer, and the third electrode are sequentially layered.