Multi-chip module with third dimension interconnect

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

1 . A multi-chip module comprising: 
 one or more processor modules, the processor modules providing one or more first buses in a first dimension; and    a memory module that couples to the processor modules using a third dimension interconnect, the memory module providing one or more second buses in a second dimension.    
   
   
       2 . The multi-chip module of  claim 1  wherein at least one of the processor modules may be replaced with a replacement module, the replacement module exposing the same logical and physical interface as the replaced processor module, and wherein the replacement module provides a different function than the replaced processor module.  
   
   
       3 . The multi-chip module of  claim 2  wherein the replacement module provides an optical interface.  
   
   
       4 . The multi-chip module of  claim 2  wherein the replacement module includes a graphics subsystem.  
   
   
       5 . The multi-chip module of  claim 1  wherein the processor module consists of a multiple processor core arranged at a periodicity consistent with memory banks in the memory module.  
   
   
       6 . The multi-chip module of  claim 5  wherein third dimension signal drivers and third dimension signal receivers are placed between the processor cores and the memory banks.  
   
   
       7 . The multi-chip module of  claim 1  wherein data is routed from a processor core included in one of the processor modules to a destination memory bank included in the memory module, the routing further comprising: 
 traversing one of the first buses until the one of the first buses intersects one of the second buses that connects to a row of memory banks that includes the destination memory bank.    
   
   
       8 . The multi-chip module of  claim 7  wherein the data is subsequently routed to the destination memory bank by traversing the one of the second buses.  
   
   
       9 . The multi-chip module of  claim 1  wherein data is routed from a source memory bank included in the memory module to a destination processor core included in one of the processor modules, the routing further comprising: 
 traversing one of the second buses until the one of the second buses intersects one of the first buses that corresponds to the destination processor core.    
   
   
       10 . The multi-chip module of  claim 9  wherein the data is subsequently routed to the destination processor core by traversing the one of the first buses.  
   
   
       11 . The multi-chip module of  claim 1  wherein one of the processor modules includes a control processor.  
   
   
       12 . The multi-chip module of  claim 11  wherein the control processor is based upon a Power Architecture.  
   
   
       13 . The multi-chip module of  claim 11  wherein at least one of the processor modules includes one or more SIMD-RISC processors.  
   
   
       14 . The multi-chip module of  claim 13  further comprising: 
 a wide on-chip bus that interconnects the control processor with the one or more SIMD-RISC processors.    
   
   
       15 . The multi-chip module of  claim 13  wherein the one or more of the SIMD-RISC processors each include a local memory that is not a cache type memory.  
   
   
       16 . The multi-chip module of  claim 13  wherein the one or more SIMD-RISC processors access a system memory by issuing direct memory access commands that specify virtual memory addresses.  
   
   
       17 . The multi-chip module of  claim 11  wherein the control processor is a PowerPC.  
   
   
       18 . The multi-chip module of  claim 11  wherein the control processor includes a reduced instruction set computer architecture with memory access governed by page and segment tables.  
   
   
       19 . The multi-chip module of  claim 13  wherein the one or more SIMD-RISC processors share memory translation and protection mechanisms with the control processor.  
   
   
       20 . The multi-chip module of  claim 1  wherein the multi-chip module includes a broadband engine architecture.