Power-up signal generator for semiconductor memory devices

Abstract

A power-up signal generator for a semiconductor memory device that uses the deep power down power-up signal for a semiconductor element, which should be in a standby state in the deep power down entry, and the power-up signal for an initialization of another semiconductor elements in a DRAM device that operates after an internal power supply voltage is generated is disclosed. The generator also uses the power-up signal, which is disabled in the deep power down entry and enabled in a deep power down exit by the internal power supply voltage. The generator may include a power-up detector for generating a power-up detection signal by means of an external power supply voltage, a deep power down power-up signal generator for generating a deep power down power-up signal in response to the power-up detection signal, a power-up signal generator for generating a power-up signal in response to the power-up detection signal and power-up controller for determining whether or not enable the power-up signal in the deep power down entry.

1 . A power-up signal generator for a semiconductor memory device, comprising: 
 deep power down power-up signal generator for generating a deep power down power-up signal by means of an external power supply voltage;    power-up signal generator for generating a power-up signal by the means of an internal power supply voltage; and    power-up controller for determining whether or not enable the power-up signal in a deep power down entry.    
   
   
       2 . The power-up signal generator as claimed in  claim 1 , wherein the deep power down power-up signal generator generates the deep power down power-up signal that is always enabled in the deep power down entry and in a deep power down exit by the external power supply voltage.  
   
   
       3 . The power-up signal generator as claimed in  claim 1 , wherein the deep power down power-up signal generator includes: 
 a divider for dividing the external power supply voltage;    a pull-up device for pulling-up a divided voltage;    a first driver for generating the power-up detection signal by the divided voltage; and    a second driver for generating the deep power down power-up signal in response to the power-up detection signal.    
   
   
       4 . The power-up signal generator as claimed in  claim 1 , wherein the power-up signal generator generates the power-up signal that is disabled in the deep power down entry and enabled by the internal power supply voltage in a deep power down exit.  
   
   
       5 . The power-up signal generator as claimed in  claim 1 , wherein the power-up signal generator includes: 
 a divider for dividing the internal power supply voltage;    a pull-up device for pulling-up a divided voltage;    a first driver for generating the power-up detection signal by the divided voltage; and    a second driver for generating the power-up signal in response to the power-up detection signal.    
   
   
       6 . The power-up signal generator as claimed in  claim 1 , wherein the power-up controller blocks the external power supply voltage in the deep power down entry and makes the internal power supply voltage from the external power supply voltage and provides it to the power-up signal generator in a deep power down exit.  
   
   
       7 . The power-up signal generator as claimed in  claim 1 , wherein the power-up controller includes a PMOS transistor with the external power supply voltage connected to a source thereof and with a deep power down mode signal applied to a gate thereof.