Level shift circuit

Abstract

In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W 3 and W 4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W 3 and W 4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N 5 , N 6 and two N-type low-voltage transistors N 1 , N 2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

1 . A level shift circuit comprising: 
 two N-type signal-receiving low-voltage transistors, which receive at their respective gates complementary first and second input signals powered by a low-voltage supply, and each of which has first and second terminals, the first terminals of the N-type signal-receiving low-voltage transistors being grounded, the second terminals of the N-type signal-receiving low-voltage transistors being connected to first and second nodes, respectively;    two N-type high-voltage transistors, each of which includes first and second terminals, which receive at their respective gates a voltage of the low-voltage supply or the complementary first and second input signals powered by the low-voltage supply, and which turn on in a complementary manner according to the first and second input signals, the first terminals of the N-type high-voltage transistors being connected to third and fourth nodes, respectively, the second terminals of the N-type high-voltage transistors being connected to fifth and sixth nodes, respectively;    a power supply circuit, which includes a first terminal connected to a high-voltage supply, a second terminal connected to the fifth node, and a third terminal connected to the sixth node, and supplies a voltage of the high-voltage supply to one of the fifth and sixth nodes, while blocking the supply of the voltage of the high-voltage supply to the other of the fifth and sixth nodes; and    a protection circuit, which includes first, second, third, and fourth terminals connected to the first, second, third, and fourth nodes, respectively, and restricts voltages at the first and second nodes to not more than the voltage of the low-voltage supply.    
     
     
         2 . The circuit of  claim 1 , wherein the protection circuit includes two N-type protection transistors each including first and second terminals, the first terminals of the N-type protection transistors being connected to the first and second nodes, respectively, the second terminals of the N-type protection transistors being connected to the third and fourth nodes, respectively.  
     
     
         3 . The circuit of  claim 2 , wherein the voltage of the low-voltage supply is supplied to the gates of the two N-type protection transistors in the protection circuit.  
     
     
         4 . The circuit of  claim 2 , wherein the complementary first and second input signals are respectively input via delay circuits to the gates of the two N-type protection transistors in the protection circuit.  
     
     
         5 . The circuit of  claim 2 , wherein the complementary first and second input signals are input directly to the respective gates of the N-type protection transistors in the protection circuit.  
     
     
         6 . The circuit of  claim 1 , wherein the protection circuit includes two protection diodes which are respectively connected to the first and second nodes at their respective cathodes and to the third and fourth nodes at their respective anodes.  
     
     
         7 . The circuit of  claim 1 , wherein the voltage of the low-voltage supply is supplied to the respective gates of the two N-type high-voltage transistors.  
     
     
         8 . The circuit of  claim 1 , wherein a stop mode signal, which is put to a low potential level when the level shift circuit is to be stopped, is input to the gates of the two N-type high-voltage transistors.  
     
     
         9 . The circuit of  claim 1 , wherein the complementary first and second input signals are respectively input via delay circuits to the gates of the two N-type high-voltage transistors.  
     
     
         10 . The circuit of  claim 1 , wherein the complementary first and second input signals are input directly to the gates of the two N-type high-voltage transistors, respectively.  
     
     
         11 . The circuit of any one of claims  1  through  10 , further comprising first and second clamp circuits, which are disposed between the low-voltage supply and the third and fourth nodes, respectively, and which clamp voltages at the third and fourth nodes to the voltage of the low-voltage supply.  
     
     
         12 . The circuit of any one of claims  1  through  10 , wherein individual threshold voltages of the two N-type high-voltage transistors are set lower than individual threshold voltages of the two N-type signal-receiving low-voltage transistors.  
     
     
         13 . A level shift circuit for receiving complementary first and second signals powered by a low-voltage supply and performing level shifting of potentials of the first and second signals to a potential of a high-voltage supply, the level shift circuit comprising: 
 two N-type signal-receiving low-voltage transistors, which receive at their respective gates the complementary first and second input signals, and each of which has first and second terminals, the first terminals of the N-type signal-receiving low-voltage transistors being grounded, the second terminals of the N-type signal-receiving low-voltage transistors being connected to first and second nodes, respectively;    a power supply circuit, which includes a first terminal connected to the high-voltage supply, a second terminal connected to the first node, and a third terminal connected to the second node, and supplies a voltage of the high-voltage supply to one of the first and second nodes, while blocking the supply of the voltage of the high-voltage supply to the other of the first and second nodes;    a power supply control circuit for controlling the power supply circuit;    a resistor for connecting the first and second nodes:    a latch circuit for latching potentials at the first and second nodes;    a disconnecting circuit, which is disposed in two ground paths going from the respective first and second nodes via the respective two N-type signal-receiving low-voltage transistors to the ground, and which disconnects one of the two ground paths and connects the other of the two ground paths;    a disconnection control circuit for controlling the disconnecting circuit; and    a protection circuit, which is disposed between the first node and one of the two N-type signal-receiving low-voltage transistors and between the second node and the other of the two N-type signal-receiving low-voltage transistors, and restricts a voltage applied between the two terminals of each of the two N-type low-voltage transistors to not more than a withstand voltage of the two N-type low-voltage transistors.    
     
     
         14 . The circuit of  claim 13 , wherein the protection circuit also functions as the disconnecting circuit.  
     
     
         15 . The circuit of  claim 13  or  14 , wherein the protection circuit is formed by disposing an N-type transistor in each of the two ground paths.  
     
     
         16 . The circuit of  claim 13 , wherein the protection circuit is formed by disposing two N-type transistors in series in each of the two ground paths.  
     
     
         17 . The circuit of  claim 13 , wherein the protection circuit is formed by disposing an N-type transistor and a diode in series in each of the two ground paths.  
     
     
         18 . The circuit of  claim 16 , wherein the protection circuit includes a clamp circuit, which connects connecting points, at each of which the series-circuit forming two devices are joined, with the low-voltage supply and clamps individual potentials at the connecting points to the voltage of the low-voltage supply.  
     
     
         19 . The circuit of any one of claims  13  through  18 , wherein one or ones of circuits other than the protection circuit include an N-type high-voltage transistor capable of withstanding the voltage of the high-voltage supply, and 
 the protection circuit includes an N-type transistor whose threshold voltage is set lower than a threshold voltage of the N-type high-voltage transistor.    
     
     
         20 . The circuit of  claim 13  or  14 , wherein the disconnection control circuit controls the disconnecting circuit based on the potentials at the first and second nodes latched by the latch circuit, so that one of the two ground paths is connected, while the other of the two ground paths is disconnected.  
     
     
         21 . The circuit of  claim 13  or  14 , wherein the disconnection control circuit receives the complementary first and second input signals and controls the disconnecting circuit based on the received complementary first and second input signals, so that one of the two ground paths is connected, while the other of the two ground paths is disconnected.  
     
     
         22 . The circuit of  claim 21 , wherein the disconnection control circuit includes two inverter circuits for inverting the complementary first and second input signals, respectively.  
     
     
         23 . The circuit of  claim 21 , wherein the disconnection control circuit includes two delay circuits for respectively delaying the complementary first and second input signals by a fixed amount of time.  
     
     
         24 . The circuit of  claim 13  or  14 , wherein the latch circuit has first and second NAND circuits; 
 the first NAND circuit receives the potential at the first node and an output produced from the second NAND circuit; and    the second NAND circuit receives the potential at the second node and an output produced from the first NAND circuit.    
     
     
         25 . The circuit of  claim 14 , wherein the disconnection control circuit, powered by the high-voltage supply, generates a high-voltage control signal, and 
 the protection circuit, which also functions as the disconnecting circuit, includes a lowering circuit for lowering the high-voltage control signal produced from the disconnection control circuit to the voltage of the low-voltage supply.    
     
     
         26 . The circuit of claims  1 , wherein individual threshold voltages of the two N-type high-voltage transistors are set lower than individual threshold voltages of the two N-type signal-receiving low-voltage transistors.