Systems and methods for epitaxially depositing films on a semiconductor substrate

Abstract

Systems and methods for epitaxial deposition. The reactor includes a hot wall process cavity enclosed by a heater system, a thermal insulation system, and chamber walls. The walls of the process cavity may comprises a material having a substantially similar coefficient thermal expansion as the semiconductor substrate, such as quartz and silicon carbide, and may include an isothermal or near isothermal cavity that may be heated to temperatures as high as 1200 degrees C. Process gases may be injected through a plurality of ports, and are capable of achieving a fine level of distribution control of the gas components, including the film source gas, dopant source gas, and carrier gas. The gas supply system includes additional methods of delivering gas to the process cavity, such as through temperature measurement devices, and through a showerhead. In one embodiment of the present invention, the system is capable of utilizing silane as a silicon source gas. In another embodiment of the present inventions the lift pin mechanism that raises a substrate off a susceptor is capable of rotating with the susceptor during processing.

1 - 23 . (canceled)  
   
   
       24 . A wafer processing system comprising: 
 a processing chamber containing a substrate holder for receiving a semiconductor substrate, the processing chamber including a top wall, a bottom wall, and at least one side wall; and    a cage-like heating assembly comprising: 
 (a) a top resistive heater positioned above the top wall;  
 (b) a bottom resistive heater positioned below the bottom wall; and  
 (c) a side resistive heater positioned behind the at least one side wall.  
   
   
   
       25 . A wafer processing system as defined in  claim 24 , wherein the top resistive heater includes at least two independently controlled heating zones.  
   
   
       26 . A wafer processing system as defined in  claim 24 , wherein the cage-like heating assembly includes at least two side resistive heaters.  
   
   
       27 . A wafer processing system as defined in  claim 24 , wherein the top resistive heater and the bottom resistive heater are enclosed in between a pair of shield members.  
   
   
       28 . A wafer processing system as defined in  claim 27 , wherein the shield members are made from a material comprising silicon carbide.  
   
   
       29 . A wafer processing system as defined in  claim 24 , wherein the processing chamber comprises a hot wall process cavity in which at least the top wall and the bottom wall of the processing chamber are made from materials that generally have the same heating characteristics as a semiconductor substrate being heated.  
   
   
       30 . A wafer processing system as defined in  claim 24 , wherein the processing chamber is configured to hold two semiconductor substrates in a side-by-side arrangement, the side resistive heater being configured to enclose both of the semiconductor substrates.  
   
   
       31 . A wafer processing system as defined in  claim 30 , wherein the side resistive heater has a peanut shape.  
   
   
       32 . A wafer processing system as defined in  claim 29 , wherein the top wall and the bottom wall are made from a material selected from the group consisting of quartz, silicon carbide, and mixtures thereof.  
   
   
       33 . A wafer processing system as defined in  claim 24 , wherein the top wall is spaced from the bottom wall a distance from about ¼ of an inch to about 3 inches.  
   
   
       34 . A wafer processing system comprising: 
 a processing chamber for receiving at least one semiconductor substrate;    a heating device in communication with the processing chamber;    a substrate holder connected to a center post, the center post for rotating the substrate holder, the substrate holder defining a plurality of holes;    a plurality of lift pins, each of the lift pins being nested in a respective hole defined by the substrate holder; and    a lift pin support plate engaged with the plurality of lift pins, the support plate being connected to a support tube, the support tube being coaxial with the center post, the support tube being movable along the center post for selectively moving the support plate up and down, wherein, when the support plate is moved upwards, the support plate causes the lift pins to rise for raising semiconductor substrates off of the substrate holder.    
   
   
       35 . A wafer processing system as defined in  claim 34 , wherein the lift pin support plate, the support tube, and the lift pins rotate with the substrate holder when the substrate holder is rotated by the center post.  
   
   
       36 . A wafer processing system as defined in  claim 34 , wherein the substrate holder is made from a material comprising silicon carbide.  
   
   
       37 . A wafer processing system as defined in  claim 34 , wherein the lift pins and the lift pin support plate are made from a material comprising quartz.  
   
   
       38 . A wafer processing system as defined in  claim 34 , wherein the heating device comprises at least one electrical resistance heater.  
   
   
       39 . A wafer processing system as defined in  claim 34 , further comprising a gas supply system for supplying gases to the processing chamber for reaction with a semiconductor substrate contained in the chamber.  
   
   
       40 . A wafer processing system as defined in  claim 34 , wherein the support tube is located on the exterior of the center post.  
   
   
       41 . A wafer processing system as defined in  claim 34 , wherein the lift pins are made from a material comprising opaque quartz.  
   
   
       42 . A wafer processing system as defined in  claim 34 , wherein the processing chamber is configured to receive two semiconductor substrates in a side-by-side relationship, the chamber including two respective substrate holders.  
   
   
       43 . A process for depositing a layer on a semiconductor substrate comprising the steps of: 
 placing a semiconductor substrate in a processing chamber;    heating the semiconductor substrate in the processing chamber; and    flowing a gas into the processing chamber, the gas flowing generally in a vertical direction and then being plenumized so as to flow over the surface of the semiconductor substrate from one side of the substrate to a second and opposite side as the substrate is rotated, the gas being partially preheated when flowing in generally a vertical direction, the gas reacting with the surface of the semiconductor substrate to form a layer.    
   
   
       44 . A process as defined in  claim 43 , wherein the gas comprises silane.  
   
   
       45 . A process as defined in  claim 44 , wherein the temperature of the semiconductor substrate is less than about 1,000° C. during formation of the layer.  
   
   
       46 . A process as defined in  claim 43 , wherein the gas comprises a chlorinated silane.  
   
   
       47 . A process as defined in  claim 43 , wherein the processing chamber comprises a hot wall chamber such that the walls of the chamber are heated to a temperature within 200° C. of the semiconductor substrate, while the semiconductor substrate is being heated.  
   
   
       48 . A process as defined in  claim 43 , wherein the processing chamber comprises a hot wall chamber such that the walls of the chamber are heated to a temperature within  100 ° C. of the semiconductor substrate, while the semiconductor substrate is being heated.  
   
   
       49 . A process as defined in  claim 43 , wherein the processing chamber has a height that is from about ¼ inch to about 3 inches.  
   
   
       50 . A process as defined in  claim 43 , wherein the flow of the gas into the chamber is selectively controlled over an edge zone, a middle zone, and a center zone of the semiconductor substrate.  
   
   
       51 . A process as defined in  claim 43 , wherein the processing chamber comprises a hot wall processing chamber, and wherein the processing chamber is preheated prior to placing the semiconductor substrate in the chamber.  
   
   
       52 . A process as defined in  claim 51 , wherein the processing chamber is preheated to a temperature that is within at least about 100° C. of a maximum processing temperature during formation of the layer.